FPGA + SRAM – floating inputs of SRAM during configuration of FPGA

configurationfloatingfpgasram

I'm connecting SRAM to FPGA (Spartan 6). During configuration and during periods when FPGA will be down (for example I would like to turn off FPGA when external flash will be programmed by uC) address lines of SRAM will not be driven, thus floating – which is bad I guess.

I came up with the idea to use a transistor to turn on / off SRAM. As I have uC on the board, I can connect base of transistor (ex. BC817) to uC and its collector to Vcc and emitter to VCCs of SRAM so I would be able to turn off SRAM when FPGA is down and when it is configured and runnign I can turn on transistor and thus SRAM.

Do you think it will be ok? Is it good idea?

Best Answer

Most of the Xilinx FPGAs have weal pull-ups that can be active before configuration. Just tie the HSWAPEN pin to ground. Floating pins for a brief period during power-on should not be a problem.