hardwarememorysram
I am now reviewing a paper about hardware implementation and it says by cropping the 128*96-pixels from 160*120-pixels, the size of the frame memory (SRAM) can be reduced to 1/10.
I don't get it.
Does anybody know how this works?
(EDITTED)
The image is first downsized to half…
So. 320*240 -> 160*120 -> 128*96
No fundamental reason why not. Synchronous SRAM is truly random access, fairly inexpensive, and easy to interface to.
Its downside in that it occupies a fairly narrow niche between the on-chip BlockRam (not much smaller, free until it forces you to select a larger chip, massively parallel and more flexible) and external DRAM (massive storage capacity at a price SSRAM can't match).
So up to 0.5 or 1MB, external SSRAM is unnecessary, and above 8MB or 16MB (numbers may vary according to your budget and current prices!), SSRAM becomes expensive enough that DRAM takes over despite its limits. Then - if you need random access - you have to massively reorganise the computation to read chunks (bursts or pages) from DRAM into BlockRam where you can process it fast before writing back bursts etc....
But if you have a role for SSRAM within that window, go for it. I have added simple home-made SSRAM boards to augment commercial FPGA platforms where necessary.
I agree that illustration is confusing.
The top half of the page is intended to describe the TLB. It sounds like you understand TLB stuff pretty well.
The entire bottom half of the page is intended to describe the data cache. (The label "cache" on the left is intended to apply to the entire bottom half of the page. How could it be redrawn to make it more obvious that it applies not only to the cache metadata valid+tag bits, but also all the data all the way to the right edge of the page?).
It suddenly splits up the physical address and uses it to index the cache, I guess.
Yes. The bottom half of that page, as you just said, and like most large caches, is a physically-indexed, physically-tagged data cache.
But why is it showing the cache and data separately?
That part of the illustration is unnecessarily confusing.
While in principle each word of memory could have its own valid+tag bits, most data caches share the valid+tag bits for a much larger block of data copied from main memory -- a block called a cache line. Loading more data than the program specifically asked for in a single instruction is often helpful, because practically all programs have some spatial locality.
The resulting cache entry structure looks something like
v tag w w w w w w w w w w w w w w w w
v tag w w w w w w w w w w w w w w w w
v tag w w w w w w w w w w w w w w w w
v tag w w w w w w w w w w w w w w w w
v tag w w w w w w w w w w w w w w w w
v tag w w w w w w w w w w w w w w w w
v tag w w w w w w w w w w w w w w w w
v tag w w w w w w w w w w w w w w w w
where the 'v' indicates the valid bit, and each 'w' represents a word of data.
Inexplicably, the book's illustration only shows one of the many blocks of data in the cache:
v tag
v tag
v tag
v tag
v tag
v tag w w w w w w w w w w w w w w w w < -- hit on this cache line.
v tag
v tag
and then the book's illustration inexplicably rotates the words in that cache line to show all the words of that one cache line stacked on top of each other.
When the data cache detects a hit -- when the cache tag matches the tag part of the desired address, and the valid bit is set -- then the "block offset" part of the address indicates one particular word of that one particular cache line.
Perhaps the illustrator ran out of room drawing an extremely wide cache line, and arbitrarily decided to rotate that line to make it fit on the page without considering how confusing that would be?
The data cache’s block size is 128 Bytes.
So for any physical byte address, the bottom 7 bits indicate some particular byte within a cache line, and all the upper bits of that address are used to select some particular cache line.
why is the byte offset just left floating?
The byte offset is left floating in this illustration, because the byte offset is not used by the TLB or by the data cache. A typical TLB and the data cache, like the one illustrated, only deal with aligned 32-bit words. The 2 bits of the address that select one of the 4 bytes within a 32-bit word are handled elsewhere.
Some simple CPUs only have hardware for aligned whole-word access. (I call them "Neither Endian" in "DAV's Endian FAQ"). Compiler writers for such CPUs must add padding to ensure that every instruction is aligned and every data value is aligned. (The two-bit byte offset should always be zeros on these machines).
Many CPUs have a LOAD instruction that can load unaligned 32-bit values into a 32-bit register. Such CPUs have special hardware elsewhere (not part of the cache) that, for each LOAD instruction (sometimes) does 2 reads from the data cache -- the unaligned 32-bit value can overlap 2 different cache lines; either or both read may cause a cache miss. The 2 bits of the address that select one of the 4 bytes within a (aligned) 32-bit word are used internally by the CPU to select the relevant bytes that the cache returns for those reads and re-assemble those bytes into the (unaligned) 32-bit value that the programmer expects. Even though such instructions give the correct results no matter how things are aligned or mis-aligned in memory, assembly language programmers and compiler writers and other programmers obsessed with optimization sometimes add padding anyway to get (some) instructions aligned or (some) data aligned or both. ("How and when to align to cache line size?"; "Aligning to cache line and knowing the cache line size"; etc.) They try to justify this padding by claiming it "optimizes" the program to "run faster". Recent tests seem to indicate data alignment for speed is a myth.
the relationship between a TLB and cache
Conceptually the only connection between the TLB and a (physically-indexed, physically-tagged) data cache is the bundle of wires carrying the physical-address output of the TLB to the physical-address input of the data cache.
One person can design a data cache for a simple CPU without virtual memory that caches physical addresses. Another person can design a TLB for a simple CPU that has no data cache (A CPU with a TLB but no data cache was once a common arrangement for mainframe computers).
In principle, a third person can splice that TLB and that data cache together, wiring the physical-address output of the TLB to the physical-address input of the data cache. The TLB neither knows nor cares that it is now connected to the data cache rather than the main memory address bus. The the data cache neither knows nor cares that it is now connected to the TLB rather than directly to the CPU address register(s).
Best Answer
If you store an image in an SRAM, generally you want to be able to split the address bus into an x and a y component. To do this, at least one of them must be a power of 2. For 320 x 240, you have to round 320 up to 512 to get a power of 2. 512 x 240 is 122880. If you shrink it down to 128x96, it's more efficient because 128 is already a power of 2 so you can fit it in a 128 x 96 = 12288 byte SRAM. There's your factor of 10.