Gnetlist Cannot Find Symbol

spice

I am trying to use gschem/gnetlist/ngspice to do some circuit simulations. I have a subcircuit schematic and have created a symbol. I am able to add the symbol into the higher level schematic in gschem but when run gnetlist I get the following error:

WARNING: Found a placeholder/missing component, are you missing a symbol file? [<symbol file name>]

The device does not appear on the output netlist. The symbol file is in a subdirectory called "symbols" and in my ~/.gEDA/gafrc I have the line

(component-library "./symbols" "Local Symbols")

as per advice on the gnetlist mailing list but for some reason it still cannot find it, though gschem finds and uses the symbol without a problem. I've tried many things but I cannot get gnetlist to find the symbol. I've scoured the Internet for an answer to no avail and I posted here because there is apparently no simple way to post the question on the gEDA mailing lists. Anyone have an idea what is going on here?

Best Answer

I found the answer to this by looking at the gnetlist log files in ~/.gEDA/logs. The problem was that I had some things in my gafrc file that were valid for gschem but were not for gnetlist. As a result gnetlist was apparently not loading the rest of the file where the component-library command was. Once I removed the gschem-only commands, gnetlist was able to load the symbol and complete without any warnings. The subcircuit components were then in the output netlist as expected.

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Find the maximum value of length and width that a PMOS or NMOS supports

The model will probably support whatever you throw at it. After all, a model is only a fancy mathematical equation - there are not usually any constraints. Without any particular context, such as a manufacturing process, there really isn't a good way to figure out an upper limit.

If you got the model from a design kit, then there would be boatloads of documentation on what specific structures the model fit was based on, and the boundaries at which the model no longer accurately portrays the device.

Since you have neither the documentation or the process that goes along with it, I can suggest some boundaries for length and width for reasonable design.

Minimum Length:   0.25 um
Maximum Length: 100.00 um
Minimum Width:    0.25 um
Maximum Width:  100.00 um

Note that you can create a larger effective width by simply adding more copies of the transistor. You can do this through the model by declaring the number of fingers, or the multiplicity of the device. This lets you get larger transistors without the downfalls of really wide gates. For a longest effective width, I'd probably say the biggest I've seen on an IC is 2,000um to 5,000um for LNA input transistors. I don't think you should need anything so large (unless you're designing an LNA).

Best Answer

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