In general, the usual answer to this sort of problem is to pipeline. You might consider adding pipeline registers immediately after the 10-bit comparators, before the logic that combines them into the enable signal for the next stage. To keep the resulting enable signal aligned with the correct data in the data path, you'll probably also need a pipeline register for the data, too.
But yes, you can also use the technique described in the other question. For your specific 10-bit counter example, instead of counting from 0 to 1003 and using a comparator to identify state 999 to turn off the enable signal, you could make it an 11-bit counter that counts from -1000 to 3. The MSB of this counter is your enable signal, and when the count gets to 3[1], you reload the counter with -1000 ... and also load an auxiliary 9-bit count-down counter with the value 249. Each time this auxiliary counter reaches -1 (MSB set) is the start of another subframe (in addition to the one that starts at the beginning of the main frame).
[1]Note that detecting "3" is a function of just 3 bits — the MSB and the two LSBs — not a function of 11 bits.
Other answers have focused on why you might be approaching this the wrong way. Although I agree with those answers, what you're asking for does exist, so I'll go ahead and give you a straight answer. You'll likely find that this approach is more expensive than alternatives though.
What you want is a 2 GHz voltage-controlled oscillator (VCO) with 3.3-V LVPECL outputs. There are many vendors out there who make such parts.
If you don't find one with LVPECL output, since this is a clock signal, it's relatively easy to adjust the levels to something compatible with LVPECL by ac coupling and rebiasing. Any rf level between -3 and +2 dBm should be usable with a LVPECL input.
LVPECL parts like your 100EP016A can also accept single-ended inputs if you bias the complementary input to the midpoint between the normal logic levels (often there's even a pin called VBB that outputs this level for your convenience, but I didn't check if the 'EP016A has it).
You will then need to build a phase-locked loop to maintain the VCO output frequency accurately by comparing it with a low-drift reference oscillator, which could be anywhere from 10 to 100 MHz.
One part that provides both the VCO and PLL in one chip is Analog Devices' ADF4360-2
A couple more notes:
I noticed that the maximum guaranteed switching frequency of the MC100EP016A is only 1.2 GHz, so if you really want to do this at 2 GHz, you might want to look for another part. Maybe MC100E137, but then you'll need to have a 5 V supply and you'll also need to deal with the unequal timing of the different outputs for a ripple counter.
Finally, you'll need to deal with latching in all the bits of the count at exactly the same instant, so you don't capture some bits before a transition and some bits after. One solution to this is to use a gray-coded counter instead of a binary counter --- then only one bit changes for any transition, and the maximum error from latching delay variation is only a single count.
Best Answer
You could build your own counter with adjustable steps in a CPLD or FPGA.
Better yet, just implement the entire DDS in a small FPGA, memory and all. There's next to no logic design work in it, e.g. Xilinx provide free DDS IP.