Open-Loop Synchronous Buck Converter – Accuracy Using Gate Driver IC

The TC4427 by itself can not generate a gate drive voltage greater than its own supply voltage. That follows from the functional block diagram on p.2 of the datasheet.

It would make the question clearer, if you add the gate driver to the schematic on the O.P. and show its supply rails.

For the time being, I'll assume that the TC4427 is powered from the same +17.4V that goes to the input of the buck. In that case, the source of the N-channel MOSFET will not be any higher than 17.4 V - V_th.

Typically, buck converters have a bootstrap gate driver¹ and an N-channel MOSFET, or a P-channel MOSFET.

¹ Bootstrap gate driver (see also here) is not the only option for N-challel MOSFETS. Other options: gate driver transformer, additional supply rail for gate driving with elevated voltage.

You should read some app notes on buck regulators.

The starting point for a buck regulator is often the inductor. A key equation for steady state of a synchronous buck is that Vout = D * Vin, where D is the duty cycle (percent high time of the switching node).

Duty cycle / switching frequency gives you the duration of the high pulse. Let's call this high time Thi.

The ripple current in the inductor is determined using V = L*(di/dt).

V is the voltage across the inductor when switch node is high (Vin-Vout). L is inductor value. dt is Thi. And di is the ripple current we are solving for.

di = (Vin-Vout) * Thi / L

If the ripple is less than twice the load current, the inductor current will never reverse. In your case, if the ripple current is less than 66mA, the inductor current will never reverse. If the ripple current is more than 66mA, then it will eventually reverse. But in a syncrhonous buck regulator, reversing current will not necessarily cause any problem (depending on the regulation scheme used). You could say that this is not going to be an efficient mode of operation, and that is for sure true. So typical regulators will do something when this happens to try to gain some efficiency.

One thing I would like to point out is that a synchronous buck, depending on the control algorithm, is potentially stable and able to maintain output voltage regulation even when the load current is negative (flowing from load into buck, instead of into load). And in this condition, the steady-state duty cycle equation is exactly the same. Vout = D * Vin.

In this case, the average inductor current will be in the reverse direction. Obviously, if current is flowing INTO Vin, it is essential that Vin be able to accommodate that current or else the voltage will start to rise.

The other point worth noting is that when the load is constant, the output voltage of a buck will always converge on Vin * D, even if there is no output voltage feedback. If you change the load current, there may be a very undesirable response (ringing and overshoot or undershoot) but it will eventually converge on Vin * D.

The output capacitor does need to be big enough to reduce output ripple voltage to a reasonable level. Otherwise none of the above analysis will necessarily apply. I am not going to go through that, though.