The sophistication of your clock gating depends on how much the downstream logic is going to respond to a bad clock pulse.
For example: If the downstream logic is always reset after the clocks switch then you can get away with almost anything for your clock gating logic.
However, if you are expecting the downstream logic to continue functioning properly when the clocks are switched (without a reset) then you gating logic must be designed so that you never have clock pulses that are too short and violate your timing constraints.
The danger with short clock pulses that violate your timing constraints is that it could put a state machine into an invalid state that it can't recover from. This is really easy to do, so don't take it for granted that it won't happen to you.
Designing good clock gating/switching logic that doesn't produce short clock pulses is difficult and usually requires intimate knowledge of your ASIC process. Rather than invent your own, I suggest that you talk with your ASIC house or whoever you got your ASIC libraries from. Odds are very high that they already have the circuit you need.
Update:
The OP indicated that the clock gates in the schematics are from the ASIC library. If those gates are designed to not glitch (I.E., they never produce a pulse that is too short), then the only trick is to allow enough time between disabling one clock and enabling the next. In this way you can cleanly switch between clocks and not have clock glitches.
Designing the logic to do this (keep enough time between disable/enable) is still difficult, but not super difficult. On a scale of 1-10, this would be a 6. Designing a glitchless clock gate, on the other hand, would be a 10 or even 12!
To answer your question, the same guidelines do not apply to ASICs and gated clocks are used very often to reduce power consumption.
In FPGAs, clock signals have dedicated routing resources that ensure low skew delivery of the clocks to fairly large areas of circuitry. If you try to gate the clock then the output of the gate will probably be forced to use normal logic signal routing resources, which can introduce significant delays and cause large clock skews. FPGAs are designed with some assumptions about how logic design should be done, and one of those assumptions is that you use clock enable signals rather than gated clocks. For common FPGAs the power consumption is enormous anyway so there is little motivation to gate the clocks.
ASICs are a much different beast. When you design an ASIC you have complete control over the gates and wires. You can safely create a gated clock and make sure that the gated clock signal is distributed properly. This is a very common technique for minimizing power consumption. For example, look at a modern microcontroller and you will see that you can, in software, turn the clock signal on and off for large chunks of circuitry such as a UART. The downside is that ASIC designers must use very expensive and sophisticated timing analysis tools to get this right.
Best Answer
Is it a bad idea to gate clocks? It depends.
In the ASIC there’s well-understood timing for clock paths, so it’s reasonable to instance a standard cell on the clock tree to gate a sub-region’s clock. On ASIC then, not only is clock gating not ‘a bad idea’, it’s widely used as a means to save power.
Not so much with the FPGA. In fact, it’s never a good idea to create gated clocks directly out of FPGA fabric logic; the synthesis tools will warn you about it if not outright forbid it. Why? The resulting inserted skew becomes impossible to manage at higher frequencies, even if the gated clock doesn’t glitch (which it will without careful design.)
This brings up a common issue: modeling ASIC clock gating on FPGAs. It isn’t really feasible to just define the clock gate in HDL and hope for the best. It needs special handing.
You can model ASIC-like gated-clock behavior in your FPGA using clock-enable flops for your synchronous blocks. This can be dealt with as a synthesis option in your flow, which will identify the gated clock domain and convert its flops to FDCEs. Vivado example: https://support.xilinx.com/s/article/982650?language=en_US
Some FPGAs do support clock gating, using dedicated clock gate resources with predictable timing and glitch-free behavior. More here from Xilinx (look for BUFGCE): https://www.xilinx.com/support/documentation/user_guides/ug572-ultrascale-clocking.pdf ; other FPGAs will be similar.
Note that with BUFGCE, you’re still obliged to meet clock setup/hold from clock enable to clock rising edge. Still, that’s an easier constraint to meet than making an asynchronous clock gate out of fabric logic. If you’re modeling an ASIC you have to account for the difference between BUFGCE and whatever standard cell you’re using in the ASIC.
Finally, you asked how clock gating is actually done. Tl, dr: the enable is latched to prevent disturbing the clock pulse with a glitch. More here: https://anysilicon.com/the-ultimate-guide-to-clock-gating/