How many NAND flash chips (measured in Gb) are required for a 32GB USB drive? What is the economic relationship between the two

There is a lot of trade-off to it.

Wikipedia also:

Despite the additional transistors, the reduction in ground wires and bit lines allows a denser layout and greater storage capacity per chip. In addition, NAND flash is typically permitted to contain a certain number of faults (NOR flash, as is used for a BIOS ROM, is expected to be fault-free). Manufacturers try to maximize the amount of usable storage by shrinking the size of the transistor below the size where they can be made reliably, to the size where further reductions would increase the number of faults faster than it would increase the total storage available.

So, NOR flash can address easier, but is not even close to as dense.

If you take at a look at a pretty decent comparison PDF.

NOR has lower standyby power, is easy for code execution and has a high read speed.

NAND has much lower active power(writing bits is faster and lower cost), higher write speed(by a lot), much higher capacity, much much lower cost per bit and is very easy for file storage use. due to it's lower read speed when using it for code execution you really need to ghost it to ram.

To quote a small section with a great table above it...

The characteristics of NAND Flash are: high density, medium read speed, high write speed, high erase speed, and an indirect or I/O like access. The characteristics of NOR Flash are lower density, high read speed, slow write speed, slow erase speed, and a random access interface.

The total number of addresses in use in the system described would be 16384+16*2^4 for a total of 16640 addresses. In order to address 16640 addresses, you need an address bus with at least 15 address lines, which could address a maximum of 32768 addresses, so 16128 addresses would be unused. This is assuming that your RAM is organized in 8 bit words and is read 8 bits at a time. If for instance, the RAM is organized as 16 bit words, then each address would access two bytes of RAM, then you would need (16k/2)= 8192+16*2^4 or 8448 addresses. Each peripheral still takes one address, but since each address of RAM is now 16 bits wide, you only need half as many addresses for the RAM, but you need 16 data bus lines. If your RAM is organized as 32 bit words, then you need 4096+16*2^4 or 4352 addresses, if for 64 bit words, 2048+16*2^4 or 2304 addresses.