I'm currently reading the book which name is "PCI Express System Architecture" and i need some answers;
1.)How PCI Express Interface sends TLPs(transaction layer packets) to device core(suppose that device is GPU)?Does PCI Express Interface raises a hardware interrupt?
2.)How Pci express device core interpret these packets?
3.)How long time needed for the next packet transmission?How the receiver and transmitter agree when to transmit and receive packets?
Best Answer
There are many layers of abstraction for PCIe interrupts. Perhaps you'd like to read about it at a low hardware level such as this xilinx core. Perhaps you'd be more interested in how an OS handles it.
Transmission latency and flow control are going to be application specific. I'd like to point out that electrically PCIe is full duplex and so flow control is entirely up to the application.
I would recommend exploring the contents of a Linux device driver.
Perhaps you can be more specific with your question. People spend their entire lives specializing in the creation of PCIe handlers.