How should I translate old TIG statement from UCF to new Vivado XDC files

No, you can't.

The .xdc doesn't control the design, it informs the tool of the physical reality of the board. Setting the clock to 100MHz or 200MHz doesn't change the design in any way, the tool will always verify that your design works with the constraint you inputted. If you forget to input constraint or input wrong constraint, you get in a situation where the tool tells you the design works when it doesn't (or vice-versa).

You have to use the clocking wizard. The input clock to the clocking wizard comes from an oscillator on the board (or another clock generated by a clocking wizard), in your case the 100MHz oscillator clock. You set the wizards's parameter for the desired output clock frequencies (2x time input clock), and voilà!

There are several reference design for your board, you should look at them to see how the core functionalities works.

A level-sensitive latch is inferred when combinational RTL doesn't assign a deterministic value to all possible combination, or the same combinational logic is assigned back to it self (i.e. default: TrigA = TrigA;). Note: for the rest of this answer when I say latch, I'm referring to a level-sentience latch. If I say flop, I'm referring to a edge-sensitive flip-flop.

The mux TrigA_i is being used as to select the D input of the latch.

The mux TrigA_i_0 is begin used as to determine if the latch should be transparent (NormalCtrl[7:6]!=2'b11) or closed (NormalCtrl[7:6]==2'b11). Functionally this mux is equivalent to a 2-input NAND gate.

There are two possible reasons the synthesizer decider to use a mux as the latch gate instead of a nand gate:

1. Balanced timing of the two paths of to the latch. A single nand gate has less propagation delay than a mux. If a nand gate were used, then a latch's enable could open or close before the data is ready which is a possible risk for a glitch. Buffers could be added for balancing propagation paths. However this may use more area and the timing difference has higher margin of error than using the same (or very similar) mux gates.
2. Less likely but still possible, the synthesizer doesn't have a great logic optimizer or there are constraints put on the synthesizer that limits optimization.

Why not use one mux whose output feeds back into itself you may ask. Muxes are not intended to be used value storage. Synthesis would have a hard time to guarantee setup/hold times to prevent meta-stability. Plus, there is also a risk of a data glitch as the select bits change form 2'b00 to 2'b11 (intermediate 2'b01 or 2'b10). Synthesizers use real latches to reduce these risks (know setup/hold requirements, non-complex inputs).

In general latches should be avoided in most RTL designs. Latches are asynchronous and therefore timing is critical to be done correctly. There are a handful of conditions where using latches is necessary. In these scenarios it is best to keep the latch as simple as possible and the gate-enable pin should be driven by a direct flop (no intermediate logic) to avoid glitches.