I'm making an ALU (Arithmetic and Logic Unit), I've made a 1-bit ALU with ease, but 1-bit (1b) is impractical, who would need only 1b? I've made that adder/subtractor and I need the comparator (multiplication/division is insane), I don't know how to make a 4b comparator (obviously). Please help!
EDIT: I have found a PURE 4b comparator, that uses 1b comparators:
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Thanks to the people that helped!
How to make a 4-bit comparator
alucomparatorlogic-gates
Related Solutions
The starting point for a problem like this is to draw out a truth table of the logic that you intend to have the circuit synthesize. Your intention is still somewhat vague even after the comments.
If we guess that the input pairs c:d and b:a are actually representing two 2-bit binary numbers then the following truth table shows the output for when c:d == b:a.
You can then add additional output columns to the table to represent the other outputs you may desire.
This should get you started. I won't present the whole final solution because you learn little from that. The mechanics for reducing the table shown for one output can be done following one of a number of known procedures including Karnaugh Maps.
Given 3 x 74LS153, consider using a 74LS153 (which is really a 2 x 4:1 multiplexers) to generate A > B and A < B given A is a 1 bit value and B is a 1 bit value and that these bits form the least significant bit pair. It can be inferred that if both A > B and A < B are false then A = B. Consider using the next 74LS153 for the next most significant bit pair. However, for this and all other bit pairs, when A = B, pass the A > B & A < B outputs of the previous 74LS153. We can repeat this (pattern) for as many bits pairs as needed. The problem is constrained to 3 pairs. I will leave the exercise of wiring up to you to complete the problem.
Regardless if you are designing combinational logic or writing software. Finding repeating patterns is usually the first step in simplifying the problem.
Best Answer
In the architectures I've looked at, the addition/subtraction operation usually sets some bits in a FLAGS or STATUS register, indicating certain conditions of the result. For example, there's often a flag bit indicating the result of the last operation was zero, or the result of the last operation was less than zero.
Notice these two flags are easilly generated with a single wide-fan-in NOR gate, and by simply checking the sign bit of the result, respectively.
The comparison operation is typically done by executing a subtraction, and throwing away the result, just leaving the FLAGS registe affected by the operation.