How to make MCLRE in CONFIG3 word work in PIC18F using MPLABX XC8

I am trying to start with PIC18 microcontrollers with a PIC18F14K50.
I am using XC8 compiler and MPLABX IDE v1.2 and I have re-checked the selected device in the project configuration.

For now, I am trying to set the configuration words. I am aware of the file below which contains the information on the configuration words.

…/Microchip/xc8/v1.00/docs/pic18_chipinfo.html

When I set the MCLRE to OFF, thus trying to disable MCLR function and enable RA3 as digital input, it seems like it doesn't set it to OFF. It stays ON all the time.

I am testing this on "Labcenter Proteus ISIS v7.9 SP1" and "mikroProg Suite for PIC by mikroElektronika". Both say that MCLRE is ON, so I cannot change this bit. Also, I cannot change the HFOFST bit which is in the same register with MCLRE in CONFIG 3. However I can set up other configuration bits.

Below is my code. Can this be a bug?

#include <xc.h> // Include the header file needed by the compiler
// CONFIG 1
#pragma config CPUDIV = NOCLKDIV    // No CPU System Clock divide
#pragma config IESO = ON            // Oscillator Switchover mode enabled
#pragma config PLLEN = ON           // Oscillator multiplied by 4
#pragma config FOSC = HS            // HS oscillator
#pragma config FCMEN = ON           // Fail-Safe Clock Monitor enabled
#pragma config PCLKEN = ON          // Primary clock enabled
// CONFIG 2
#pragma config BOREN = ON           // Brown-out Reset enabled and controlled by software (SBOREN is enabled)
#pragma config BORV = 30            // Brown-out Reset Voltage set to 3.0 V nominal
#pragma config PWRTEN = ON          // Power-up Timer Enabled
#pragma config WDTPS = 1            // Watchdog Timer Postscale Select bits 1:1
#pragma config WDTEN = OFF          // WDT is controlled by SWDTEN bit of the WDTCON register
// CONFIG 3
#pragma config MCLRE = OFF          // RA3 input pin enabled; MCLR disabled
#pragma config HFOFST = OFF         // The system clock is held off until the HFINTOSC is stable.
// CONFIG 4
#pragma config DEBUG = OFF          // Background debugger disabled, RA0 and RA1 configured as general purpose I/O pins
#pragma config STVREN = ON          // Stack full/underflow will cause Reset
#pragma config XINST = OFF          // Instruction set extension and Indexed Addressing mode disabled (Legacy mode)
#pragma config BBSIZ = OFF          // 1kW boot block size
#pragma config LVP = OFF            // Single-Supply ICSP disabled
// CONFIG 5
#pragma config CP0 = ON             // Block 0 code-protected
#pragma config CP1 = ON             // Block 1 code-protected
#pragma config CPD = OFF            // Data EEPROM not code-protected
#pragma config CPB = OFF            // Boot block not code-protected
// CONFIG 6
#pragma config WRT0 = OFF           // Block 0 not write-protected
#pragma config WRT1 = OFF           // Block 1 not write-protected
#pragma config WRTB = OFF           // Boot block not write-protected
#pragma config WRTC = OFF           // Configuration registers not write-protected
#pragma config WRTD = OFF           // Data EEPROM not write-protected
// CONFIG 7
#pragma config EBTR0 = OFF          // Block 0 not protected from table reads executed in other blocks
#pragma config EBTR1 = OFF          // Block 1 not protected from table reads executed in other blocks
#pragma config EBTRB = OFF          // Boot block not protected from table reads executed in other blocks

void main(void)
{
    TRISC = 0x20; // RC0: Out / RC1: Out / RC2: Out / RC3: Out / RC4: Out / RC5: In / RC6: Out / RC7: Out
    LATC = 0; // Clear PORTC output latch.
    ANSEL = 0; // All analog inputs are disabled and made digital.
    ANSELH = 0;

    while (1)
    {
    }
}