How to protect the SMPS feedback voltage divider from loading effects

^{simulate this circuit – Schematic created using CircuitLab}

Here's an example, see if this makes sense.

Consider the circuit on the left. Assume the meter VM1 is perfect- it has infinite input resistance. The voltage VM1 measures is \$ 10V \cdot \$ \$R2 \over (R1 + R2) \$ = 5V

Consider the circuit on the right. The meter VM2 has an input resistance of 1M represented by an ideal meter in parallel with 1M ohms. The equivalent resistance of R4 in parallel with R5 is R4||R5 = \$ R4\cdot R5 \over (R4 + R5) \$ = 90.909K ohms. The voltage VM2 reads is then \$ 10V \cdot \$ \$R4 || R5 \over (R3 + R4 || R5) \$ = 4.76V

The loading down of the 1M resistance reduced the reading by about 5%.

If you've been doing Thévenin equivalents, this should come as no surprise, since the unloaded divider could be replaced by a 5V source with 50K in series, and 1M is 20 times the source resistance.

Yes, you definitely need to consider the input resistance and/or bias current requirements of the ADC input.

The usual technique is to keep the Thévenin resistance of your divider low enough that the offset caused by the ADC input is "low enough" (e.g., less than 1% or 1 LSB), depending on your system requirements.

For example, suppose that your ADC input resistance is 1 MΩ and you want to keep the error caused by this to less than 1%. Therefore, the Thévenin resistance of your divider should be less than 10 KΩ.

So, now you have two equations, one for the divide ratio:

$$Ratio = \frac{R1}{R1 + R2}$$

and one for the resistance:

$$R_{TH} = \frac{1}{1/R1 + 1/R2}$$

and two unknowns, R1 and R2. It's straighforward math to plug in your known values for Ratio and R_TH and solve for R1 and R2.