How to reduce voltage from a high speed buffer

level-shiftingsignal integrityvoltage divider

I am using this buffer to connect signal between 2.5 V and 5.5 V to a 3.3 V microcontroller.

The problem is I will get a 5 V output and my microcontroller doesn't have 5 V tolerant inputs so I have to reduce it to 3.3 V. The perfect solution would be something like this. It has double power supply, one for input voltage and the other for output voltage so level conversion is easy. But in my country (Argentina) it doesn't exists and buying it at international shops would be expensive (we have lots of taxes).

So, I have the first chip with 5 V outputs and my microcontroller needs 3.3 V. I was thinking of a simple voltage divider with resistors on each output, but the buffer is bi-directional and that will decrease the input voltage to the input.

So I thought of using 1N4148 diodes connected to a power supply of 3.3 V – Vdiode in order to activate the diode if the voltage exceeds 3.3 V. I need a resistor to limit the current in that case? I have clock signals of about 35 MHz, would that affect my signal?

Best Answer

Ok, the only way I could achieve this was asking for samples of 74LVC8T245. 40MHz is considerably high frequency to easily reduce input voltage.