Independence of the two channel architecture of LPDDR4


I'm working on a project involving LPDDR4. I've read the pertinent sections of the recently released JEDEC LPDDR4 spec. I have several questions regarding the independence of the two channel architecture. These answers to these questions may be self-evident to those with a strong knowledge of DDR, but this is my first experience with it. My questions are:

  1. Are the mode registers per channel or per device?

  2. Do CK_t/c_A and CK_t/c_B need to be the same frequency? If not, how different can they be?

  3. Are CA_A and CA_B completely independent or are they intended to be identical?

Best Answer

  1. MRs are per channel. Some of the calibration to do with SDRAM is per channel.
  2. It is not necessary that CK_A and CB_B has to be same. May be same, may be different.
  3. Both the channels are independent of each other.

The only advantage is that both the channels are on same die.