Interfacing 62256 SRAM to low pin-count AVR via latches

atmegaavrsram

I need to add over 20 kBytes of RAM to the small device built around ATMega8. Moreover I'm interested to research whether I can substitute it with ATtiny2313. The goal is roughly speaking to store some fast arriving data there before serving them out through serial interface…

I thought of 62256 chips, but with them I need 15 address lines and 8 data lines – somewhat more than I can spare with any of these two MCUs. Meanwhile the matter is to find the solution with smallest (cheapest) MCU possible, so I'm not ready to switch to some ATMega16 or 32 which, I think, will do the trick. I also have found serial SRAM from Microchip, but it seems the speed will be not sufficient for me…

So I'm thinking of using two (?) octal latches – but I'm afraid I'm reinventing the wheel and here could be easier solution. That's why I'm here. This is my current idea:

  • I feed the high and low bytes of the address from outputs of two octal latches;
  • I wire 8 pins (say, PB0..PB7) to both latches and to 8 data lines;
  • Now I need two more pins to control latches and another two for WE and OE of the SRAM chip.

And here are my questions:

  • are two latches enough, is it correct I need no latches on data lines?
  • will 74hct373 be a good choice for latches?
  • is it ok to slightly swap address lines for high byte (i.e. instead of order A8, A9, A10, A11, A12, A13, A14 wire them as A8, A9, A11, A10, A14, A13, A12 for example to simplify routing)?
  • perhaps there is another solution (besides larger MCU, latches or serial SRAM) I've missed?

Best Answer

Sounds OK. You are correct, don't put a latch on the Data lines as these are bidirectional. As long as you make sure OE is deasserted when you are programming the address, and you your latch enable lines are never asserted when OE is asserted, then you shouldn't have any problems. It will take additional clock cycles to access the memory, but that's the price you pay for saving pins.

It would basically be something like:

  1. Ensure OE and WE are deasserted
  2. Load address 0..7 onto data lines
  3. Latch into the lower address latch
  4. Load address 8..15 onto data lines
  5. Latch into upper address latch
  6. Either load data onto data lines (for write), or set to input (for read)
  7. Perform operation using OE and WE pins.

Swapping the address lines to the SRAM would be fine - it just means stuff will be stored in a weird order inside the SRAM, but as far as the uC is concerned it will be contiguous. For flash this can be an issue as page accesses would no longer be possible, but SRAM like the 62256 doesn't have that issue as it doesn't use paging.

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