Ise complaining index out of range, but it seems to be in range

I'm righting a vhdl module that calculates the LPCs from incoming DT samples.
My ise editor is complaining that my index is out of range. Is there any reason anyone can see that it should be complaining about this here?

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

use IEEE.NUMERIC_STD.ALL;
use work.LPC_pkg.ALL;


entity signature_extract_1 is
    Generic(    num_coefficients: integer:=12;
                num_samples_per_window: integer:= 80);
     Port ( samples_in : in  STD_LOGIC_VECTOR (7 downto 0);
              start_calc_flag : in  STD_LOGIC;
              sample_address : out  STD_LOGIC_VECTOR (15 downto 0);
              lpc_feature_value : out  coeff_matrix;
              lpc_feature_number : out  STD_LOGIC_VECTOR (4 downto 0);
              feature_complete : out  STD_LOGIC;
              all_complete_flag : out  STD_LOGIC;
              sample_clock: in STD_logic
              );
end signature_extract_1;


architecture Behavioral of signature_extract_1 is

signal sample_count: Integer:=0;
signal R: std_logic_vector(15 downto 0):=(others=>'0');
signal past_sample_array: past_array;
signal T: auto_corr_matrix;
signal coefficients: coeff_matrix;
component matrix_mult is
generic( num_coefficients: integer);
port( auto_corr_values: in auto_corr_matrix;
        coefficient: out multiplicand_type;
        index_k: in integer);
end component;

begin

coefficients_calc:process(sample_clock, start_calc_flag)
                        begin
                            if start_calc_flag = '1' then
                                sample_count<=0;
                                R<=(others=>'0');
                                T<=(others=> (others=>'0'));
                                past_sample_array(sample_count)<=(others=>'0');
                            elsif rising_edge(sample_clock) then
                                if sample_count=0 then  
                                    R <= std_logic_vector(unsigned(samples_in)*unsigned(samples_in));
                                    T(0)(15 downto 0) <= R;
                                else                
                                    for k in 0 to num_coefficients-1 loop
                                        exit when k = sample_count;--prevents coefficient of (n-x) form being calculated before sample n=x hads been received
                                        R <= std_logic_vector(unsigned(samples_in) * unsigned(past_sample_array(sample_count-k))); --multiplying the input sample by the delayed sample
                                        T(k) <= std_logic_vector(unsigned(T(k)) + unsigned(R)); --this is line 81, summing all values of pase coefficient(k) with new value from new input*delayed input(k)
                                    end loop;
                                end if;
                                past_sample_array(sample_count)<=samples_in;
                                sample_count <= sample_count+1;
                            end if;
                        end process coefficients_calc;


GEN:    for i in 0 to num_coefficients-1 generate
            matrix_multx: matrix_mult   generic map (num_coefficients=>num_coefficients)
                                                port map (auto_corr_values=>T,coefficient=>coefficients(i),index_k=>i);
        end generate GEN;


--Coefficients are given in reverse order, with coefficient(p) being the first in the array and coefficient(0) bring in the last place
lpc_feature_value<=coefficients;


end Behavioral;

here is the package for the types

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
package LPC_pkg is

constant num_coefficients:integer:=3;
constant num_samples_per_window:integer:=1;


subtype multiplicand_type is std_logic_vector(32+num_samples_per_window*2-1 downto 0);
subtype auto_corr_val_type is std_logic_vector(16+num_samples_per_window-1 downto 0);


type multiplicand_matrix is array(num_coefficients-1 downto 0) of multiplicand_type;
type past_array is array(num_samples_per_window-1 downto 0) of std_logic_vector(7 downto 0);
type auto_corr_matrix is array(num_coefficients -1 downto 0) of auto_corr_val_type;
type coeff_matrix is array(num_coefficients -1 downto 0) of multiplicand_type;

end LPC_pkg;

package body LPC_pkg is

end LPC_pkg;

There are two parts to my module, the autocorrelation part which is the process in the main module shown here, and a for gen statement that generates a a module with nested for gens. figured the latter isn't necessary for this question but if it is I can put it up.

xilinx's complaints are (errors)

Line 81: Index value <3> is out of range [2:0] of array <t>
Line 81: Index 3 is out of array constraint 2 downto 0 for target t

both for the module shown here.

what is it complaining about because it seems to me that the index's are in the expected range?

Thanks, your help is always appreciated!

UPDATE:
line 81 is noted in both the original code now and is copied down below

T(k) <= std_logic_vector(unsigned(T(k)) + unsigned(R)); --summing all values of pase coefficient(k) with new value from new input*delayed input(k)