LPC43xx External Static Memory – Multiplexing of Address/Data lines

Presumably the FPGA has some purpose for its SRAM connection, though you haven't specified what that is. I would guess that your best bet would be to have a means by which the Cortex can sufficiently influence how the FPGA writes to SRAM, and find out enough about what it's reading, to determine whether the SRAM is working properly. For example, if the FPGA would normally write the SRAM with data captured received from an ADC, and output it, after a delay, to a DAC, one could have a test mode that would instead write data from a linear-feedback-shift register, and another test mode that would mix data read from the SRAM into a linear-feedback-shift register with slightly different taps. If one can arrange to have each test mode run through the SRAM a controlled number of times, initializing the LFSR before the first pass and reading it after each pass, one can arrange things so that it would be unlikely a broken SRAM would yield the correct LFSR values, but the hardware could be simpler than allowing the CPU direct access, and (more importantly) the access timings would be like those the SRAM would see in actual use.

If you want to figure it out the first step I would do is lay out the ranges as bits

         1111 11
         5432 1098 7654 3210
         -------------------
0x1000 = 0001 0000 0000 0000 serial
0x100F = 0001 0000 0000 1111

0x1010 = 0001 0000 0001 0000 parallel
0x101F = 0001 0000 0001 1111

0x8000 = 1000 0000 0000 0000 memory
0xFFFF = 1111 1111 1111 1111

Now based on the comment you made "A15 - A4 are the bits that matter and A3-A0 are dont cares." It makes me think that you only need to select whether it goes to memory, serial or parallel. We don't care about telling the difference between the min or max of a range, only that we are inside the range. So what we need to do is detect if bits that are unique to the entire range.

If you look at the above chart, we can see we can tell the difference between a Serial and parallel by checking if bit 4 is set. Now to tell if we are using one of the IO or if we are using memory we need to see if bit 15 is set.

We can see this easier if we mask off the bits that don't effect us

         1111 11
         5432 1098 7654 3210
         -------------------
0x1000 = 0XXX XXXX XXX0 XXXX serial
0x100F = 0XXX XXXX XXX0 XXXX

0x1010 = 0XXX XXXX XXX1 XXXX parallel
0x101F = 0XXX XXXX XXX1 XXXX

0x8000 = 1XXX XXXX XXXX XXXX memory
0xFFFF = 1XXX XXXX XXXX XXXX

So we just need 2 bits to be able to choose the device we want, your multiplexer would look like this

         MUX
      -----------
 A4 --| 0    00 |--- Serial
      |         |
      |      01 |--- Parallel
      |         |    ___
A15 --| 1    10 |---\   \
      |         |    |   >--- Memory
      |      11 |---/___/  
      -----------   (^--- That is a OR gate)

Accessing something not in one of the 3 defined ranges will give "undefined behavior". If you don't want undefined behavior, then you need to define it! What will happen when I attempt to access a address in the range of 0x0020 to 0x7FFF?

Here is a full schematic of the original setup, I could not make thicker lines for the buses, Just assume the A0 on one side matches to A0 on the other. CS is Chip Select.