I want to know that if I want to enable the MAM Function in lpc 2468 should i specify both the MAMTIM AND MAMCR registers or only MAMCR.
Is it necessary to specify MAMTIM along with MAMCR for enabling the
working of MAM
MAM means MEMORY ACCELERATOR MODULE which is used to enhance the performance of ARM processor.
MAMTIM means MAM TIMING REGISTER which determines how many CCLK's are used to access Flash memeory.
MAMCR means MAM CONTROL REGISTER which determines the operating mode of MAM.
MAM has three operating modes:
- MAM disabled
2.MAM partially Enabled.
- MAM fully Enabled.
LPC2468 datasheet here – 85 pages.
User manual here – 792 pages !!! 🙂
Best Answer
Manual seems to clearly say:
You need both MAMCR and MAMTIM
Without MAMCR 'it does not hunt'.
Without setting MAMTIM it appears to hunt randomly.
MAMCR
2 bits in MAMCR control what MAM operating mode is used.
The default setting = 00 which is MAM disabled.
01 partially enables MAM functions and
10 enables all MAM functions.
11 is for when you are feeling bored and wonder what colour smoke it will make. They provide it just to make you curious.
MAMTIM
3 bits in MAMTIM set flash access cycle count.
User manual around page 105 says:
7.1 MAM Control Register (MAMCR - 0xE01F C000)
Two configuration bits select the three MAM operating modes, as shown in Table 6–99. Following any reset, MAM functions are disabled. Software can turn memory access acceleration on or off at any time allowing most of an application to be run at the highest possible performance, while certain functions can be run at a somewhat slower but more predictable rate if more precise timing is required.
Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of Flash information as required. This guarantees synchronization of the MAM to CPU operation.
7.2 MAM Timing Register (MAMTIM - 0xE01F C004)
The MAM Timing register determines how many CCLK cycles are used to access the Flash memory. This allows tuning MAM timing to match the processor operating frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash accesses would essentially remove the MAM from timing calculations. In this case the MAM mode may be selected to optimize power usage.
ADDED
Question:
sir u want to say that specifying only MAMCR=0x02 will not make the MAM work ?
2 - MAM fetch cycles are 2 CCLKs in duration what does it mean
ANSWER
I want to say, read the manual and user guide in detail and see what all the registers are said to do.
That is a VERY complicated IC and you must be prepared either to spend the time understanding it, or use something else.
I have never used this part - I am just used to reading data sheets. It says that if you set MAMCR it WILL work but, IF I read the user guide correctly, it will use the number of clocks per cycle based on MAMTIM contents which are not defined according to this.
They MAY have been defined somewhere else but you need to know this.
The default may work Ok BUT you need to know this.