I have a 4 to 1 mux that receives its data inputs and select inputs from edge clocked shift registers . Also the output of the mux goes to another shift register(call it the output register) as well. Should the clocking of all these register be synchronous or should I clock the data input and select registers on the leading edge of the clock and clock the output register on the falling edge of the clock? What's the ideal way of doing this?
Multiplexer Timing
multiplexer
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Best Answer
Synchronous clocking works well. Prop delay of mux must be less than one clock cycle and output will be delayed one clock cycle from input.