Verilog – Nested Parallel Blocks

verilog

I executed the following code on vcs:

module test;
  
reg v,y,a,b,p,m;

  initial

    begin

      v = 1'b0;

      #5 y = 1'b1;

      fork

        #20 a = v;

        #15 b = y;
join
      
#40 v = 1'b1;
      
fork
  
#10 p = v;
  
begin
  
#10 a = y;
  
#30 b = v;
  
end
  
#5 m = y;
  
join
      
end
  
initial
  
  $monitor($time, "\n v=%b y=%b a=%b b=%b m=%b  p=%b \n",v,y,a,b,m,p);

endmodule

The console gives the following output:

Compiler version S-2021.09; Runtime version S-2021.09;  Oct 24 03:00 2022
                   0
 v=0 y=x a=x b=x m=x  p=x 

                   5
 v=0 y=1 a=x b=x m=x  p=x 

                  20
 v=0 y=1 a=x b=1 m=x  p=x 

                  25
 v=0 y=1 a=0 b=1 m=x  p=x 

                  65
 v=1 y=1 a=0 b=1 m=x  p=x 

                  70
 v=1 y=1 a=0 b=1 m=1  p=x 

                  75
 v=1 y=1 a=1 b=1 m=1  p=1

What's the significance of using the 'begin and end' statements in the second fork block?

Best Answer

A fork block executes all statements within it in parallel.

A begin block executes all statements within it in sequence.

Here is the 2nd fork block with different whitespace layout:

fork
   #10 p = v;
   begin
      #10 a = y;
      #30 b = v;
   end
   #5 m = y;
join

In this fork block, 3 threads are run in parallel (all 3 start at the same time):

The 1st statement: #10 p = v;
The begin block
The last statement: #5 m = y;

The 2 statements inside the begin block run in sequence. The 1st statement in that block delays simulation by 10. The 2nd statement delays by 30, for a total of 40. b is assigned to v 40 time units after the fork starts.

Without the begin/end block, 4 statement would run in parallel. b would be assigned to v 30 time units after the fork starts.

Related Solutions

Electronic – Procedural blocks in verilog

Does that affect the timing of these signals?

Not really.

Yes a&b are evaluated sequentially but in the same simulator timestep, not seqential in terms of electronic design.

initial begin
  a = 1'b0;
  b = 1'b1;
end

a and b are essentially evaluated in parallel. but your simulator can not do that, the only time that this needs careful consideration is if you rely on previous results.

The following are just examples and would imply latches in some case and should not be used in RTL like this.

always @(posedge clk) begin
  a = y;
  b = a; //this is b=y
end

is not the same as:

always @(posedge clk) begin
  b = a;     //This is old y
  a = y;
end

For clocked systems (implying flip-flops) we use non-blocking (<=) the following 2 examples are the same:

always @(posedge clk) begin
  a <= y;
  b <= a; //this is old y
end

always @(posedge clk) begin
  b <= a;     //This is old y
  a <= y;
end

Electrical – Verilog loop for multiple always blocks

I learned […] every reg needs to have his own always block…

I think you've got this backwards. Each register should only be assigned to by one always block. However, this doesn't mean you need a separate always block for each register! It's perfectly safe (and, in fact, quite normal) to have a single always block for all the synchronous logic in a module, e.g.

always @(posedge clk) begin
    if (reset) begin
        A <= 4'b0;
        B <= 4'b0;
        …etc…
    end else begin
        …etc…
    end
end

What if I have a loop, lets say something like this:

You can't do that in a loop.

Verilog loops are for generating multiple copies of repeated logic. They are not a substitute for clocked logic -- if you need to perform multiple actions, you will probably need to make them happen on separate clocks, and implement them in a state machine.

Depending on what you need to happen, there might be some way to "unroll" the loop and make several iterations happen in a single clock. However, you will need to be very careful about how you implement this. Making multiple levels of branching logic run in a single clock cycle is generally inadvisable; data dependencies will severely limit the clock rate of such a design.

Best Answer

Related Solutions

Electronic – Procedural blocks in verilog

Electrical – Verilog loop for multiple always blocks

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