Elementary, Watson. You sortof had the idea with #2, except that you don't want a negative gain but rather a gain between 0 and 1. In other words, you want to attenuate the 0-15 V input signal to match the input range of your A/D.
This is easily accomplished with two resistors in a "resistor divider" configuration. If your A/D has a native range of 0-5V, then you want to divide the input voltage by 3. This can be accomplished, for example, with 2K Ohms in series followed by 1K Ohms to ground.
Anything you do to a signal will always change it slightly. In this case, some of the high frequencies will be lost. However, at impedances of 10s of K Ohms, this won't be a problem with a sample rate of 1KHz or less. That implies a upper frequency limit of 500Hz maximum, rather less in practise. Even 100s of K Ohms used in the resistor divider should be able to pass such low frequencies without losing the part you care about.
What is the ADC Clock?
The section that you are seeing is for the clock used for the ADC. This clock is not directly related to the max sampling frequency though. The clock is what is actually being fed to the ADC module which needs to be faster than your sampling so that it can handle some magic for you.
How does the Max clock relate to the max sampling frequency?
What the datasheet is saying is that in order to get 10 bit resolution your clock can not be any faster than 200 KHz. When your clock is at that speed, you will be able to sample your signal at 15,000 samples per second.
If you don't need all 10 bits of resolution then you can provide the ADC with a faster clock and you will get a faster sampling rate, but the datasheet is not clear as to how fast you can go and still get 8 bit resolution.
I would assume that the clock to sample rate ratio is fixed, so 200K/15K = 13.33 which means you can go as low as 50 KHz clock resulting in 3.75 kSPS.
Why a minimum clock to get a 10 bit sample?
The ADC module is doing a sample and hold in which the voltage is essentially held in a capacitor. If you slow the clock down too much, the voltage can start to bleed off of the capacitor before a complete sample is performed. This change in voltage makes it such that you can't get all 10 bits accurately.
So what does this all mean?
According the the Nyquist-Shannon sampling theorem your sampling frequency needs to be at least twice the maximum frequency in your signal. You can learn more about why by looking at this question: Puzzled by Nyquist frequency
So in order to get 10 bits of resolution, the max your signal can be is 7.5 KHz, but if you need to sample a signal faster than that, you can, but the datasheet does not mention how high you can go or how much it hurts your resolution.
Best Answer
What you are asking for is a non-linear operation, so will add distortion.
The details are all in the tradeoffs you haven't told us about, particularly response time. For example, suppose there is a loud passage, then it gets quieter. What metric do you use to decide this quiet isn't part of the signal that you want to keep, like a person pausing between words? Are you allowed to look ahead (store signal, then play back later)? If not, how long is long enough to decide that quiet is the new normal? Notice that you don't get to say "instantly", since audio is iherently AC, which will have regular zero crossings.
People have been dealing with these issues and making these tradeoffs in various ways for a long time, before there were even transistors. Look up something called AGC (automatic gain control).
Otherwise, without a real spec, there is little we can help with.