If the ripple-carry adder is fewer gates and satisfies timing constraints, why should the synthesizer not prefer it? In many cases, the most efficient way to generate a carry chain is to use a mixture of ripple-carry and lookahead units. For example, if one is implementing a 32-bit adder with a 16-gate-delay timing budget, rendering it as two eleven-bit sections and a ten-bit section may require fewer gates than the fastest possible arrangement while still meeting the timing requirements.
I'd suggest figuring out how to play with timing constraints; I would guess you'd find that independent of whether you design in a ripple-carry or carry-lookahead adder, the mix of ripple- and lookahead-carry generated by the compiler would vary with the constraints specified. If you wish to maintain a particular arrangement of carry logic, you can explicitly tell the compiler that you want certain signals generated (since this is a fictional design anyway, routing them to I/O pins might be a good way to do that). I suppose a compiler might still decide to ignore the P and G signals even if it was forced to generate them, but hopefully it would be smart enough not to do that.
Not with only the standard AND, OR, and NOT gates. For the two-bit adder that takes in two-bit numbers AB and CD, and outputs a three-bit number XYZ, the truth table looks like this:
A B C D | X Y Z
0 0 0 0 | 0 0 0
0 0 0 1 | 0 0 1
0 0 1 0 | 0 1 0
0 0 1 1 | 0 1 1
0 1 0 0 | 0 0 1
0 1 0 1 | 0 1 0
0 1 1 0 | 0 1 1
0 1 1 1 | 1 0 0
1 0 0 0 | 0 1 0
1 0 0 1 | 0 1 1
1 0 1 0 | 1 0 0
1 0 1 1 | 1 0 1
1 1 0 0 | 0 1 1
1 1 0 1 | 1 0 0
1 1 1 0 | 1 0 1
1 1 1 1 | 1 1 0
The Karnaugh map for Y looks like this:
CD AB>
V 00 01 11 10
00 0 0 1 1
01 0 1 0 1
11 1 0 1 0
10 1 1 0 0
The problem is that since you are only allowed two gate delays, and we need both of those: one to AND together the bits in each group, and another to then OR those groups together. This means that the groups we can specify are limited to those that do not contain any NOTs, i.e. only the following:
A B C D A*B A*C A*D B*C
. . x x . x x . . . . . . . . . . . x . . . . . . . . . . . . .
. . x x . x x . . . . . x x x x . . x . . . . . . . x x . . . .
. . x x . x x . x x x x x x x x . . x . . . x x . . x x . x x .
. . x x . x x . x x x x . . . . . . x . . . x x . . . . . x x .
B*D C*D A*B*C A*B*D A*C*D B*C*D A*B*C*D True
. . . . . . . . . . . . . . . . . . . . . . . . . . . . x x x x
. x x . . . . . . . . . . . x . . . . . . . . . . . . . x x x x
. x x . x x x x . . x . . . x . . . x x . x x . . . x . x x x x
. . . . . . . . . . x . . . . . . . . . . . . . . . . . x x x x
Note that none of these groups covers the 1001 spot without covering the 1101 spot, which we need for Y. You may be able to get the correct groups using a NAND, NOR, or XNOR; but only if those count as 1 gate delay.
Note that if you are using a technology like CMOS logic where each bit has an inverse available, then using the Karnaugh map technique renders this problem trivial, with an example solution below (where a is NOT A, etc.):
X = AC + ABD + BCD
Y = Acd + abC + Abc + aCd + aBcD + ABCD
Z = bD + Bd
Best Answer
Here is a 4-bit ripple carry adder (taken from here):
The number of gates for each bit in each full adder is 5. The number of gates just for the carry logic is 3. So the total number of gates for 32 bits would be 5 * 32 = 160. There are also plenty of circuits on the web that use 6 gates instead of 5, e.g. this one, which would be 6 * 32 = 192 gates, and the number of gates just for the carry logic is 4.
The difference between the two circuits, is that the first one (above) uses the output of the first XOR as one of the inputs to the OR gate for the carry. In the second circuit, the carry input to the OR gate is derived directly off of the A and B lines.
What this means is the the first circuit will be two gates delays slower than the second because of the XOR. For the first circuit,, the gate delays to generate a final result will be 2 * N + 2, where N is the number of bits. (2 * N because of the AND and OR gates.) For the second circuit, just 2 * N.