Clock Gating – Method of Clock Gating with a Latch

clockclock-gatingdigital-logiclatch

My textbook (CMOS VLSI Design: A Circuits and Systems Perspective, 4th edition, by Weste and Harris) gives the following discussion of a particular method of clock gating into some digital block.

I am trying to understand Figure 5.7 in particular. The somewhat parsimonious explanation given for the method is, again, below:

The clock enable must be stable while the clock is active (i.e., 1 for systems
using positive edge-triggered flip-flops). Figure 5.7 shows how an enable latch can be used to ensure the enable does not change before the clock falls.

Why does this "work how we want it to"? The clk signal is doing its usual 50% duty cycle square wave action, and the active-low Enable Latch therefore maintains the output of the Enable Logic block while clk is high. But what would be the problem without the Enable Latch? Is the idea that if the Enable Logic went back high and we didn't have Enable Latch, then we might get violations on the registers (I guess these wouldn't be called hold or setup time violations since the Clock Gater output is not a data input, but a clock input to the registers) around the positive edge of the clock? How does the Enable Latch preclude this? Is this the issue being solved by it?

Best Answer

The latch-based clock gate logic helps to prevent glitches on the clock output signal from the clock gate, assuming appropriate timing constraints are applied when synthesizing/implementing the design.

Narrow clock pulses can produce timing violations in the register (flip-flop), which typically has a minimum clock pulse width requirement.

Here are some example waveforms where the input signals to the clock gate are en and clk.

Let's assume there are 2 types of clock gate for comparison:

AND-based: a simple AND gate, with output cg_and
Latch-based: similar to your Figure 5.7, with output cg_lat

As shown in the waves at time 75ns, cg_and has a very narrow pulse (glitch), whereas cg_lat does not.

Related Solutions

How do data and address strobes cause input to be latched

In clocked systems, the "strobe" signal is treated as an "enable" signal for the corresponding latch or register. In other words, the data is captured on any clock edge for which the strobe or enable is active. This means that the timing is strictly relative to the clock edge, but the strobe indicates which clock edges are relevant.

Electrical – Introduce delays of alternating value for synthesis on hardware

From the other question, you already have a way of delaying the signal by between 1 and 4 clock cycles:

reg[3:0] bits;

always @ (posedge clk_27)
begin
    vsync_o <= bits[3]; //this was in the original code but actually makes it 5 cycles! But whatever.
    bits <= {bits[2:0], vsync};
end

So you can easily modify that to have two signals coming out, one with 4 cycles delay and the other with 2 cycles delay (hint: if bit 3 is 4 cycles of delay, which bi is 2 cycles).

Now you have two signals - one with 4 cycles of delay, and one with two cycles of delay. All that is needed then is a way to select which one is which. The word "select" implies you need a multiplixer - 2:1 in fact (two signals in, one out).

That means you also need something to drive the select line. Given it is 2:1, this is just a 1 bit control signal which you need to toggle every time there is a pulse. What do you know that can toggle? A flip-flop. To you need a flip-flop that toggles every time there is a pulse on Vsync.

The next question is, how do you detect a pulse on Vsync? Well, you see if there is a rising edge (or falling edge, or both). For that you need a rising edge detector. The structure is essentially:

reg delay;
always @ (posedge clock) begin
    delay <= in;
end
wire risingedge = delay && !in;
wire fallingedge = !delay && in;
wire bothedges = delay != in;

So you need the signal, plus the signal delayed by one clock cycle. You have vsync, and your bits register has the signal delayed by one clock cycle, so you already have all the signals you need to build an edge detector.

reg whichDelay;
always @ (posedge clock or posedge reset) beign
    if (reset) begin
        whichDelay <= 1'b1; //Start with a delay of 2 because on the first rising edge we will toggle.
    end else if (vsync && !bits[0]) begin
        whichDelay <= !whichDelay; //Toggle on each vsync input
    end
end

assign vsync_o = whichDelay ? bits[1] : bits[3];

And there you have it.

Best Answer

Related Solutions

How do data and address strobes cause input to be latched

Electrical – Introduce delays of alternating value for synthesis on hardware

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