Operational Amplifiers problem

Like you said, the fact that the two opamp inputs will be nearly equal is a simplification and depends on parameters often not explicitly stated. This is a good question in that it is essential to know the limits of any shortcuts or rules of thumb you use.

As clabacchio already said, one place the assumption are violated is if the opamp output is clipped, or would need to exceed its available range to make the desired signal. Other reasons that make the assumption invalid include:

1. The feedback isn't negative. This may sound stupid, but I've actually shown someone a simple opamp hysteresis circuit in a interview and asked them to draw a plot of output voltage as a function of input voltage. More than one candidate started off saying the opamp will try to keep its two inputs the same, and then dug himself into a deeper hole from there. Needless to say, those were short interviews.

2. The gain isn't sufficient. Note that the rule of keeping the inputs equal assumes infinite gain. Likewise the rule that Gain = -Rf / Rin assumes infinite gain. Normally opamp open loop gains are around 100k or more and we don't ask for more than 100 or maybe 1000 at most from a single stage, so it would seem this is a small issue.

   However, that forgets about the effect of frequency on gain. A 1 MHz opamp may be specified for 100k open loop voltage gain at DC, but if you use it for audio and want to pass 20 kHz, then you only have a open loop gain of 50 worst case. If you set the feedback resistors for a gain of 25, that only leaves 2x headroom at the high end, which will seriously reduce closed loop gain at high frequencies.

3. Slew rate limitation. Even with enough gain and proper feedback, the opamp can only change its output so fast. That is what the slew rate spec is for. The gain*bandwidth product is for small signals. Large amplitude signals may run into slew rate issues. For most opamps, the full swing output signal is rather lower frequency that what the gain*bandwidth product implied.

The way this is drawn we can ignore I1, Q2 and R4 and write:

Vout = \$V_B(1+\frac {R_3}{R_2})\$

\$V_B = -V_T ln(\frac {Vin}{R_1 I_S}) \$, if Vin > 0 and 0 if Vin < 0

Where Is ~= 0.026V at room temperature and Is is saturation current of the transistor. This follows directly from the Ebers-Moll model equation Ic \$\approx I_S e^{\frac {V_{BE}}{V_T}}\$

For example, suppose R1 = 10K, Vin = 5V, Vt = 0.026V, Is = 6.73fA , then Vb = -.651V.