PCB Design – Optimal 4-Layer Stack Up for High-Density Board

emcpcbpcb-designsignal integritystack up

I have a question about designing a stack up for a 4-layer PCB with a high-density top layer. I know the optimal way to generally do this is to go for either 1 or 2 as these stack ups provide a good return path.

(1)         (2)    (typical)

—sig/pwr— — GND — — sig —

— GND — —sig/pwr— — GND —

— GND — —sig/pwr— — pwr —

—sig/pwr— — GND — — sig —

However, the problem with figure 1 is that I can't route power or do a power pour on the top layer since, as I have said, there are too many components and signal traces, and the PCB can't be expanded.

Furthermore, figure 2 would cause the GND plane to get sliced up too much as a result of the components.

Is it OK to go with the typical stackup if I always place a return via (connected to GND) next to a via connecting the top and bottom signals? There will not be many vias connecting the top and bottom layers because the bottom of the PCB is pretty bare, but it must remain that way.

For reference, this is a low-speed DC circuit which I know means I could probably get away with simply going for the typical stack up, but I want to develop best practices to reduce EMI.

Best Answer

For reference, this is a low speed DC circuit which I know means I could probably get away with simply going for the typical stack up, but I want to develop best practices to reduce EMI.

What I'm describing below is required for high-speed circuits. It's probably not required for DC circuits. I'm writing this answer only because the O.P. is asking for best practices - in general.

What I wanted to know is if it is ok to go with the typical stackup if I always place a return via (connected to GND) next to a via connecting the top and bottom signals?

That would work for the options (1) and (2) stack-up, but not for the (typical) stack-up.
In the (typical) stack-up, the signals on the bottom layer are referenced to a ground plane, and the signals on the bottom layer are referenced to the power plane. A simple stitching via connected to GND can't simply connect to a power plane, because it would be a dead short power to ground. It's still possible to provide a high frequency return path if the stitching via is connected to GND, and the side of the via is connected to power plane through a capacitor.

That would be a lot of capacitors. That's why contemporary high speed designs rarely use power planes as reference planes. Speeds are getting higher, and PCB layers are getting cheaper.

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