Powering LED strip and Raspberry Pi from a single 10A 5.5V power supply

I'm going to be wiring the rows up snake style and dual feeding to keep brightness consistent across the array.

If Dual Feeding is what I think it means, you already know what to do.

Feed the 5v to each 106cm section individually or in pairs. Don't chain the power through the entire 17m length. Sure, this means 8 or 16 sets of 5v and Gnd cables, but with each only carrying 2A or 4A over a small length, heat/current/resistance issues go away. Same reason you only see 18 AWG wire in ATX Power Supplies. Instead of a single 10AWG 12v Cable, it uses 8 or 12 18AWG wires to carry the same current.

You would keep the data cable the same. Just make sure to tie the grounds together.

Actually, pretty much how the datasheet for the Sparkfun item you linked to already has it, for a snake layout.

For 1M strips (106cm = 1.06M) the voltage drop would be insignificant.

Rather than needing line buffers, I suspect that your string is just too long from a power point of view. The strip power and ground traces are simply too thin to carry 30 amps successfully.

I suggest that you find some way to access the power and ground traces (particularly the ground) at 3 meter intervals, and solder a 16 ga wire to each access point. Run the wires back to the power supply. Make sure you insulate the solder joints. At the very least you should be able to access the lines at each end of the strip, which would be better than nothing.

EDIT - With the inclusion of your scope traces, it's pretty clear that you're out of luck. The lower trace indicates that the chip has very slightly slower low-to-high propagation time then high-to-low. This means that, over many successive transmissions a positive pulse (or the positive portion of your clock) will gradually get narrower and narrower. As has happened to you.

But it's not the manufacturer's fault. Look at your numbers. With an 8 MHz clock, it's high for about 60 nsec. Your lower trace shows that your clock pulses have shrunk to almost nothing - call it 10 nsec. This means that you have a propagation delay imbalance of 50 nsec/1500, or 33 psec. Trust me, there's no (single-ended) process which can guarantee better performance.

For what it's worth, a reconnaissance satellite camera had similar problems which were traced to Altera FPGAs which had imbalances of several nsec, and the imbalance was stated in the data sheet. The cure was to invert the clock between each stage so that the imbalances cancelled each other out. Obviously, this isn't an option for you.

As I stated, I'm afraid you're out of luck. The manufacturers apparently never forsaw someone trying to extend their strips to the extent which you're doing.