Prevent loss of Large Signal Voltage Gain at low Rload

I think the keyword is "loop gain" - and the most important point (as far as stability is concerned) is the frequency where the loop gain Alo is unity (0 dB).

Because the loop gain is the product of the amplifier´s open-loop gain Alo and the feedback factor Hr (Alo=Hr*Aol) you can find the BODE diagram for the loop gain response very easily:

Draw Aol=f(w) and 1/Hr(w) as a BODE plot and the difference between both curves gives you the loop gain Alo (in dB). The stability criterion requires that at the frequency where both curves meet (Alo=0 dB) the phase shift of the loop gain must not equal to (or even more than) 180 deg.

That means: The "rate of closure" (slope) of the loop gain at this crossing frequency must not be -40dB/dec. (Rule of thumb: If the second pole is identical to the frequency with Alo=0 dB we have app. 45 deg phase margin).

Based on this requirement you can derive the necessary/desired location of the second pole.

Remark ("It's often said that the more feedback the better"): You strictly must distinguish between DC and dynamic stability. Heavy feedback improves the stability of the operating point but - at the same time - degrades the dynamic stability (against oscillations).

EDIT: Sorry for the large picture. I don´t know if/how the size could be reduced.

1. Response is low at low frequencies because \$C_1\$ blocks low frequency signals from reaching the input of the amplfier.

2. Response is low at high frequencies because of parasitic capacitances within the MOSFET. A typical small-signal model of a MOSFET looks like this:

(Image source: QSL.net)

Typically, the most important parasitic for limiting the high-frequency response is \$C_{gd}\$. The gain in the circuit multiplies the effective value of this parasitic, by what's known as the Miller effect.

The main effect of \$C_{gd}\$ is to provide a negative feedback from the output node to the gate node.

Cds can also be important. In an ac equivalent circuit, it is essentially in parallel with the output capacitor (\$R_D\$ in your diagram), reducing the overall output impedance, and thus the gain, at high frequencies.