Preventing Reset during ESD

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I would like to design a RC filter to prevent reset to a SoC during a ESD strike. Assuming the reset net is by default low.

And the reset comes from a separate board which connects to the main board (where SoC resides) using a Board to Board connector.

In case there is air discharge on the daughter board. I want to avoid changing the state of reset line during the ESD strike and avoid trigger of reset to the SoC.

Best Answer

Assuming the reset pin is pulled up, putting a 100nF cap to ground at the pin generally won't hurt you. The bigger issue here is ESD protection. Where is the ESD getting into the circuit? Cable shields, connectors, the enclosure, any user interface buttons or knobs, , etc. all need to be considered. The energy from the event needs to be safely dissipated, with the how depending on the source. I strongly recommend read through John Barnes' articles on ESD protection.