Quartus Gives Undefined Signal For the State of a Finite State Machine. Supposed to Be Showing Enum of the State_type

quartus-iisimulationvhdlwaveform

Before beginning a larger project in Quartus II I'm trying to do the section 8.8 "FSM as an Arbiture Circuit" example from the book "Fundamentals of Digital Logic with VHDL Design 3rd ed" and I can't get Quartus to work like it's supposedly documented. The Machine State Variable which is a VHDL SIGNAL in the FSM's Architecture won't show as anything other than Undefined, even though the FSM is working fine.

Here is a screenshot of the Finite State Machine Implemented in Quartus:

http://i.stack.imgur.com/XtzCn.png

The book, in a different example shows the FSM's state just fine. The Machine State is the Y variable, which is showing an ENUM like Quartus is supposed to.
enter image description here

I've even followed the directions provided by Altera in the below linked pdf. The directions for this are on pages 27 to 29. I've followed them exactly but that SIGNAL is still showing up as undefined no matter what. Am I missing something?
ftp://ftp.altera.com/up/pub/Altera_Material/11.0/Tutorials/VHDL/Quartus_II_Simulation.pdf

Best Answer

This is definitely a Quartus II issue. I'd suggest you you delete state from the simulation display and re-add it insuring it matches Figure 29 on Page 29 of the tutorial you provided the link for, above.

I wrote a test bench that reproduces the waveform from the book. You can use it to insure the arbiter works as intended even if you can't display state:

library ieee;
use ieee.std_logic_1164.all;

entity arbiter_tb is
end entity;

architecture foo of arbiter_tb is
    signal clk:        std_logic := '0';
    signal reset:      std_logic := '0';
    signal r:          std_logic_vector(1 to 3) := (others => '0');
    signal g:          std_logic_vector(1 to 3);
begin
CLOCK:
    process 
    begin
        wait for 50 ns;
        clk <= not clk;
        if Now > 1150 ns then
            wait;
        end if;
    end process;

DUT:
    entity work.arbiter
        port map (
            clk => clk,
            reset => reset,
            r => r,
            g => g
        );

STIMULUS:
    process
    begin
        wait for 51 ns; 
        reset <= '1';
        r <= (others => '1');
        wait until rising_edge(clk) and g(1) = '1';
        r(1) <= '0';
        wait until rising_edge(clk) and g(2) = '1';
        r(2) <= '0';
        wait until rising_edge(clk) and g(3) = '1';
        r(3) <= '0';
        wait;
    end process;

end architecture;

And this is as close as I could get with ghdl and gtkwave:

arbiter_tb gtkwave display

If re-adding state didn't work you'll need to find Altera specific help.

Related Solutions

VHDL Finite State Machine Pattern Checker

There are several issues with your code. My rewritten version is below.

The main problem is that your code was that the assignment of Z was incorrect. The next problem was that the state machine itself was incorrect. As it was written, Z should have gone high after a pattern of "11", and not "110". It also would have gotten stuck in state S2 and not recovered.

I should also mention that there were several "stylistic" issues with your code too. Having two processes instead of one was a major one. I cleaned up that as well. This allowed for having only a single state signal, which makes the whole thing more readable as well.

 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;

 entity checker is
   Port ( clk : in  STD_LOGIC;
            x : in  STD_LOGIC;
            z : out STD_LOGIC);
 end checker;    

 architecture Behavioral of checker is    
   type state_type is (S0, S1, S2);
   signal state: state_type := S0;
 begin

     process(clk)
     begin
       if rising_edge(clk) then
         case state is 
             when S0 => 
                z <= '0';
                if x='1' then 
                  state <= S1;
                else 
                  state <= S0;
                end if;

             when S1 => 
                z <= '0';
                if x = '1' then 
                  state <= S2;
                else 
                  state <= S1;  -- S1, not S0 because we also want to detect a "111...1110" 
                end if;

             when S2 => 
                if x = '0' then
                  state <= S0;
                  z <= '1';  -- Z='1' only when a match is made
                else
                  state <= S0;  -- Goes back to S0 to detect the next pattern
                  z <= '0';
                end if;

             when others => 
                z <= '0';
                state <= S0;  -- In case the state machine is in an invalid state 
         end case;
       end if;    
     end process;

   end Behavioral;

Update: Here's a rewritten testbench:

library ieee;
use ieee.std_logic_1164.all;

entity testbench is
end testbench;

architecture arch_testbench of testbench is
  component checker
    port (clk   :in  std_logic;
          x     :in  std_logic;
          z     :out std_logic);
  end component;

  signal clk    :std_logic := '1';
  signal x      :std_logic := '0';
  signal z      :std_logic := '0';

  signal sr     :std_logic_vector (15 downto 0) := "0001100011111110";
begin

  process (clk)
  begin
    if clk='1' then
      clk <= '0' after 5.0 ns, '1' after 10 ns;
    end if;
  end process;


  process (clk)
  begin
    if rising_edge(clk) then
      sr <= sr(sr'high-1 downto 0) & "0";
    end if;
  end process;

  x <= sr(sr'high);

  UUT:  checker
      port map (clk, x, z);

end arch_testbench;

Call a Finite State Machine in VHDL

A FSM is a sequential piece of circuitry, and functions are combinational only, so a function cannot represent by itself a FSM. However, the combinational paths of the FSM can be represented with functions. Typical examples are coding the next state or the outputs based on the current state and inputs. It is a very clean way of coding a FSM.

A procedure, on the other hand, can contain sequential statements, but when they do they are mostly used for testbenches using wait statements, which are not synthesizable.

Best Answer

Related Solutions

VHDL Finite State Machine Pattern Checker

Call a Finite State Machine in VHDL

Related Topic