\$V_{gs}\$ defines the thickness of the channel under the Gate (in a 3D mosfet model). Think of this channel as a hallway whose width you can increase as you increase \$V_{gs}\$. Think of people walking through the hallway as electrons ( \$I_{d}\$). Think of yourself as a god who can force people to have to run through this hallway (force = applied \$V_{ds}\$, which creates \$I_{d}\$)
If the hallway is wider (\$V_{gs}\$ is higher), you can fit more running people (electrons) before people start getting stuck in a tight trafficy environment (current saturation).
If you keep the hallway constant (\$V_{gs}\$ is constant), the there is only a finite amount of people (finite \$I_{d}\$) you can force (increase \$V_{ds}\$) before people start getting stuck and jammed up (\$I_{d}\$ saturates). If you try to force more people into the jammed hallway (try to increase \$I_{d}\$ by increasing \$V_{ds}\$), you will barely be able to. It will be a lot harder for you because the doorway is already jam-packed (\$I_{d}\$ = saturated) with people (current).
I like to think in analogies because all of these phenomena are already experienced by us in everyday life. This analogy gives a rough idea of whats happening under the hood. :) Hope it helps!
This is an example of DTL (diode-transistor logic). The Minuteman II missile, designed in the early 1960's, used 2000 DTL and DL IC's in its guidance computer. Diode logic (DL) performed its functions with just diodes and resistors, but since it lacked transistors for signal restoration you couldn't cascade many circuits together (or invert a signal).
Here is the truth table for an AND gate:
A B out
0 0 0
0 1 0
1 0 0
1 1 1
Now lets look at that in terms of voltages:
A B junction of R1 and R2
gnd gnd 0.7 Q1 off, Q2 on (x = 0.7v)
gnd Vcc 0.7 Q1 off, Q2 on (x = 0.7v)
Vcc gnd 0.7 Q1 off, Q2 on (x = 0.7v)
Vcc Vcc ~Vcc Q1 on, Q2 off (x = ~Vcc)
If either or both inputs A or B are ground (or close to it), the diode(s) associated with the grounded inputs will conduct, causing the voltage of the junction between R1 and R2 to be at around 0.7v, the forward voltage drop of the diodes.
Therefore the base voltage will be too low to turn Q1 on. The base of Q2 will be near Vcc, so it will turn on and the output X will be low, near the Vbe of Q1.
If both inputs A and B are near Vcc, both diodes will be reversed biased. The junction of R1 and R2 will then be near Vcc, and Q1 will turn on. This will put a near ground (Vbe of Q1) on the base of Q2, turning it off. So the output will then be high, near Vcc.
An OR gate is very similar. The diodes just face the other way, and R1 is connected to ground instead of Vcc.
Here is the truth table for an OR gate:
A B out
0 0 0
0 1 1
1 0 1
1 1 1
Now lets look at that in terms of voltages:
A B junction of R1 and R2
gnd gnd 0.7 Q1 off, Q2 on (x = 0.7v)
gnd Vcc Vcc-0.7 Q1 on, Q2 off (x = ~Vcc)
Vcc gnd Vcc-0.7 Q1 on, Q2 off (x = ~Vcc)
Vcc Vcc Vcc-0.7 Q1 on, Q2 off (x = ~Vcc)
If either of the inputs are high, then the associated diode will be forward biased, and the voltage at the junction of R1 and R2 will be equal to the Vcc minus the diode drop.
The remaining analysis (what the output is depending on the voltage to the base of Q1) remains the same as for the AND gate.
Best Answer
OK first a little on notation. Your Vgs(off) is also called the Threshold voltage (Vt) and the pinch-of voltage (Vp), I think they all mean the same thing. The voltage where the device is off.
So I cracked open "Art of electronics" (2nd ed.), They talk about two regions of operation. A linear region where the the drain current is proportional to the gate source voltage.
Id ~ (Vgs-Vt) and a saturation region where the current is proportional to the square of that voltage.
Id ~ (Vgs-Vt)^2.
The details are involved. You might read some here.. and then look up the references.