As you can see in the image, I'm running the example given in here where I would debounce the limit switch. I'm running the SN7414 with the given resistors in the diagram. The problem here is that with the calculated resistors, I'm still getting a 0.818V across the capacitor, and from the datasheet, the SN7414 will only switch to logic high when the voltage is at the minimum 0.6V.
The guide talked about input leakage current (Ii), which turns out to be 1mA for the SN7414. I measured the current going towards the SN7414 when the limit switch was closed turns out to be 130uA which causes a theoretical biased voltage of 1.066V but the measured voltage is 0.829V. This prevents the SN7414 from reaching it's negative going threshold… which prevents the SN7414 from triggering a rising edge.
In the guide, they used a 74AHCT14 where the Ii = 1uA… this is substantially smaller than in the SN7414.
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Am I looking at the right place as to why there is a potential across the cap after the switch is closed?
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How do I compensate for this? I can lower the value in R2 by using a 10uF cap.
Note: ignore the "0.733V when switch is closed" in the diagram, that was when R2 = 4.7kohms
Best Answer
You have chosen the SN7414. If you look at the schematic in the data sheet page 3, you will see that internally there is a 6K ohm resistor tied high to Vcc and then through a diode to the input pin A of the 7414. So your capacitor is being charged up by the input from the 7414.
Either use the 74AHCT14 (or equivelant) or reduce your resistors to values low enough that your resistors can soak up the (almost) 0.8 mA (edit, I originally said 8mA incorrectly) from the 7414. Meaning your R2 needs to be a lot smaller.