To answer your last question first. THe source is defined by what terminal you connect your bulk connection. So no, there is no difference in the S/D until that connection is made. However, different process technologies impose different connections. In a typical CMOS (now-a -days) the substrate is using <100> P-type. Which means that the bulk is always connected to ground for NMOS (NMOS transistors are built in P-type wells). The PMOS, (built in N-Wells) can have a "floating" bulk connection because the N-Well to P-substrate will be reverse biased. For a PWell in P-sub connection (NMOS) you can see there is a direct connection.
MOS transistor gates are capacitors, when there is a voltage imposed on the gate (lets only talk about NMOS here, PMOS is the inverse) say a +'ve voltage. Electrons are attracted to the other "side" of the capacitor plate (this happens to be the channel) to balance the charge. the channel has p-dopants in it which when the voltage is applied get ionized by the E-field. This is what establishes the channel. The positive potential at the surface drives the holes away from the surface, leaving it depleted. The charge that is in the channel that equates the gate charge is due to the uncovered acceptor atoms (p-dopants).
As the gate voltage increases, the substrate can be seen to move through three separate regimes. The first (at low E-Field levels) the substrate is enhanced there are lots of majority carriers (holes). As the voltage increases the substrate goes into depletion and finally as the voltage increases further the substrate inverts and the channel connects to the electron reservoirs at the S/D ends. These regimes also correspond to the regimes of operation (roughly) as sub-threshold, triode and active regimes of operation.
This also explains the capacitance change of the gate wrt Vgb or Vgs (for S=D). Below the threshold, the charge on the gate sees the acceptor atoms which are distributed in depth, so the opposite electrode to the capacitor looks almost "fuzzy" to it. i.e. the effective E-field can be thought to penetrate a little further, which decreases capacitance. Once the channel is established, all those electrons are gathered up close to the surface, the distance between plates is decreased and the capacitance is increased.
So, you reverse the bias and the battery begins pulling electrons out of the N type silicon and holes out of the P-type silicon *, eventually the area around the junction becomes charged up like a capacitor and the current stops flowing.
(*) you could picture this as filling the holes with electrons, but either way because of the electric field of the battery the holes move to the metal, and then accepting an electron from the metal, they disappear.
Best Answer
AFAIK the statement that energy levels actually bend is wrong. We are just extrapolating diagrammatically to show how the two conduction bands and valence bands are linked with a space charge region in between.
Lets just consider the case of a pn-junction. First, when the two parts, p and n are not forming a junction, then, you will agree that the fermi level shifts upwards and downwards in the p and n type materials from the middle position of energy band gap? How? Take the case of an intrinsic material where number of electrons in the conduction band will be equal to the number of holes in the valence band. This means that the overall energy balances somewhere in the middle of the forbidden band gap. Thus, for an intrinsic semiconductor, the fermi level lies approximately at (Ec+Ev)/2. Now, when we dope it with a pentavalent impurity, thus creating an n-type semiconductor, we are effectively adding more electrons in the conduction band than there are holes in the valence band (owing to the extra discrete energy level inserted by the dopant near the conduction band) Thus, the balance of energies tilts in favor of the conduction band and the fermi level now lies somewhere closer to the valence band. Similarly, the fermi level for a p-type semiconductor lies near the valence band.
Now, let us create a junction with these two types of semiconductors. By creating a junction, we create a concentration gradient and that results in diffusion. How long would this continue? As long as there is graident, or there is some force that can equally oppose this process of diffusion across the junction. But what does that equilibrium condition mean in terms of energy? When no more diffusion can take place, it basically means that the fermi levels of both p-type and n-type materials are now equal (since unequal energy levels creates a gradient?) Thus, the Fermi levels of the two materials are equal. But what we did there was to reduce the fermi level from the center of band gap in case of p-type and raise it above in case of n-type. Thus, for an electron to jump from the valence band of the p-type material to the conduction band of the n-type material, it now needs energy that is equal to the total displacement of fermi levels, i.e. downward shift on p-type fermi level plus upward shift in n-type fermi level. This is the minimum energy that must be provided to the electron through external bias (forward bias) for the junction to conduct and would be called the barrier potential. So, I think, it is not the forward bias that causes the bend, forward bias just helps cross this small barrier or hill. The bend is due to the shift of fermi levels and as a consequence, the entire energy profile of the n-type material shifts downwards, relative to the p-type material (because both will have the same fermi level)
I hope this helps, it is a little difficult to visualize things in text.