I need use an shift register, but instead of the typical serial in/parallel out, the inverted functionality, parallel in/serial out. So, there is an several options, like the MC74HC165A. My plan is use two of them and tied to MISO line, but this chip can't put it's output to high-impedance state, so what happens with the MISO line?? I guess that if the MC74 force it's output to LOW, the other slaves on the bus can't be able to TX, right?
If I chain the output of the shift register with an 3-state buffer, would work?
Thank you!
Best Answer
First of all be aware of the phase of the SPI signals.
A SPI usually clocks and then samples the line, while the shift register always outputs the MSB and shifts on clock; so you'll miss the first bit unless you can reconfigure your master to one of the odd phases;
You are right, you can't tie together two pushpull CMOS outputs; in fact you risk damaging them.
Your idea of a 3s buffer is correct, a 74xxx1G125 would be a good part with the OE tied to the CS. Alternatively you could use a shift register which already has a 3s output, if it existed in the 74 lineup, I mean :D
The PCA9703 is more or less that but it's a far more complex part (it's also more SPI friendly)