Operational Amplifier – Slew Rate of Two Stage OTA

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I have learnt two stage opamp designing from books and yourtube videos, but have always failed to understand slew rate formula which is I5/Cc(I5 is bias current of M5 and Cc is compensation capacitor). Always thought that slew rate should depend on load capacitor and not compensation capacitor. After thinking a lot I finally simulated by giving opposite phase square wave to input and looked at all current values. It looks like the load capacitor is getting charged by second stage PMOS and discharged by second stage NMOS. It seems like the contribution of current from first stage is very small. If this is true shouldn't the slew rate be a function of current of second stage transistors and load capacitor?

I have attached one image for your reference, the up arrow means voltage is going from zero to vcc and the down arrow means voltage is going vcc to zero.
Slew rate of OTA

Best Answer

If this is true shouldn't the slew rate be a function of current of second stage transistors and load capacitor? Yes.

In a two stage miller compensated op amp, slew rate is a function of input bias current and compensation capacitance and is often used to design the operational amplifier in texts.

However, you should be able to see that if the load capacitance is dramatically increased beyond the internal compensating capacitance, then the ability to maintain the same slew rate (measured at the output under an external load capacitance) requires either larger current in the input stage or larger current in the output stage. There has to be enough total current to drive a total max load capacitance and maintain a targeted slew rate.

"Normally, slew rate is not limited by the output, but by the current sourcing/sinking capability of the first stage." Allen, Holberg. Analog Ciruit Design 2nd edition.2002

"The overall slew rate is either limited by the first stage or the second stage, whichever is slower. The proper bias current can be determined by SPICE simulation" Silveria, VLSI systems on a chip, 1999