Is your transformer secondary 12 turns *total* or 12 turns on *each side* of the center tap? If it's the former, that's why you can only get 30 V under load. I calculate it this way:

Input voltage is 220 V_{RMS} full-wave rectified to about 310 V_{DC}.

This means that your half-bridge is driving the transformer with a voltage whose peak is half of this, or 155 V.

The 33:12 transformer is going to turn this into a peak voltage of about 56 V.

If the secondary is center-tapped, then you're only hitting the rectifiers with a peak of 28 V.

As for the excessive rise at low loads — well, that's why lots of SMPS specify a minimum load. It's actually quite difficult to design an efficient one that also has a huge dynamic range. One problem might be excessive leakage inductance (i.e., less than perfect coupling) in your transformer.

EDIT: Since I can't put this drawing in the comments, I'll add it here. Your transformer drive waveform *always* needs to be symmetric. At 50% duty cycle, it should look like a square wave, with a small amount of "crossover distortion" created by the dead time:

```
-------- --------
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
-------- --------
```

But at lower duty cycles, it still needs to be symmetric, with longer "off" periods between the alternating pulses. It should look like this:

```
-- --
| | | |
| | | |
| | | |
| | | |
- ------ ------ ------ --
| | | |
| | | |
| | | |
| | | |
-- --
```

This is the sort of waveform that the drivers on the SG3525 are designed to produce.

Just at first sight, your formula gives an energy (Joule), not power (Watt)...

If the "*...custom equipment has an oscilloscope which is monitoring the voltage across the inductor and the current through it...*", then the inductor losses can be calculated right out of the measured values (i.e. right from definition of average power) as:

\$ P_{losses} = \frac{1}{T} \int_0^Tv(t)i(t)dt \$, (average value of instant power during period)

where *v*(*t*) is the waveform of voltage across the inductor, *i*(*t*) is the waveform of current through it and *T* is period of these waveforms. Provided that the oscilloscope is a digitizing equipment, then, in principle, the corresponding voltage and current samples from within one period have to be multiplied, summed, multiplied by the sample interval and divided by the period (*T*) length.

For instance the trapezoidal integration method can be used:

If there are *n* equidistant samples (of \$ v_i, i_i \$, i = 1 to n) covering one period T, then the losses can be calculated as:

\$ P_{losses}= \frac{1}{(n-1)} \cdot (\frac{{v_1} \cdot {i_1} + {v_n} \cdot {i_n}}{2}+ \Sigma_{i=2}^{n-1} v_i \cdot i_i) \$

2015-04-12, \$ \textbf 1^{st} \$ **appendix**

As I already stated in the very beginning, your formula is not okay. At first, the *T* in it is superfluous (it is already incorporated in the *duty cycle*, *D*). Let's have a look at it a bit more closely. It can be rewritten (omitting the *T*, of course) as:

\$ P_{AC} = [D \cdot (V_{IN}-V_{OUT})-(1-D) \cdot V_{OUT}] \cdot I_{RIPPLE} = (D \cdot V_{IN}-V_{OUT}) \cdot I_{RIPPLE} \$,

but is it already okay?

You wrote "…*Since the inductor has some AC losses from eddy current and hysteresis, I took the power during the charging period and subtracted the power during the discharge period and what would be left is the loss…*".

In principle, this idea is right in my opinion, but:

- The voltage across
*L* during \$ t_{ON} \$ (term with *D* multiplier) is:
\$ V_{L\_on} = V_{IN}-V_{PMOS\_SWITCH\_ON}-V_{OUT} \$,

not just \$ V_{IN}-V_{OUT} \$ (the PMOS switch contribution isn't negligible).
- The voltage across
*L* during \$ t_{OFF} \$ (term with (1-*D*) multiplier) is:
\$ V_{L\_off} = -(V_{OUT}+V_{DIODE\_SWITCH\_ON}) \$,

not just \$ -V_{OUT} \$ (neither the diode switch contribution is negligible).
- If we presume both the above voltages as constants during their time intervals and the ripple current being "
*pure*" sawtooth waveform, then value that must be used in the calculation on the place of current is \$ I_{RIPPLE}/2 \$ (i.e. its average value – it follows from the very first formula, because if *v*(*t*) = const., then it can be factored out the integral and the rest is the ripple current average value).

The resulting formula will be then:

\$ P_{AC} = [D \cdot V_{L\_on}+(1-D) \cdot V_{L\_off}] \cdot \frac{ I_{RIPPLE}}{2} \$

( \$ V_{L\_off} \$ is negative in relation to \$ V_{L\_on} \$, we have to measure both the voltages the same way, that's why the "+" operator is used in the formula)

It is questionable, however, whether the speculated presumptions (3) are "sufficiently" valid/met and how much they affect accuracy of the result.

## Best Answer

The inductance is merely a requirement of the switched frequency. Also a higher inductance usually means higher package/device size for a given current rating. What you should be worried about is not the Henries, rather the actual current carrying capacity and saturation point of the inductor used.

Your boost converter's inductor should have a current rating (and saturation point) easily 1.5x times more than your intended output current. Ripple currents for boost converters can be quite high, so make sure your output and input capacitors have suitable ripple current ratings and low-ish ESR (their ability to handle ripple current, they get hot due to ESR).

Google around for some application notes on SMPS boost converter design, they will cover the important aspects for selecting and sizing inductors appropriately. I know that Microshop and Texas Instruments both have good ones i've seen before. here is one from TI on basic calculations for a boost converter's power stage.

Also note that having inductances x3 more than required can very heavily damp the start-up current and settling time of the SMPS control system