Static Hazard and challenging questions

Assuming the decoder is active, the Truth table is as follows :

XZ    Dec_Out    HA1        HA2    a b cin    F G
               Sum | C    Sum | C
00   1000      1     0    0     0  1 1 0      0 1
01   0100      1     0    0     0  1 1 0      0 1
10   0010      0     0    1     0  0 1 1      0 1
11   0001      0     0    1     0  0 1 1      0 1

The truth table is easy to construct :

• First determine the output of decoder corresponding to various inputs
• Next apply D0 and D1 as inputs to HA1 and D2 and D3 as inputs to HA2
• Compute their outputs and apply them to FA

Now since it was a competition problem, there has to be a short cut (which I was not able to figure out initially as well) instead of solving the truth table :P

• Two outputs of a decoder cant be simultaneously high. This means that the sum of both half adders cant be one simultaneously. Infact, output of exactly one HA HAS to be 1 always, and also that both have to give a carry of zero.
• The Xnor will always give a 1, since both carry are always zero.
• If 2 of the inputs to the Full adder are always one, the sum ie F will always be 0, while the carry ie G will always be 1.

Similar arguments hold when decoder is inactive, but this time output of both HA will be 0.

• With outputs of both half adders as zero, the XNOR is still high while A and Cin are zero
• So the input of FA consists of exactly one, which means sum ie F will always be 1 while carry ie G will always be 0.

In either case, F and G are always complements to each other.

The answer is that there is not enough information in the question to decide between the two possibilities.

If you assume that \$\overline{A}\$ is generated by an inverter fed from \$A\$, that the gates have the same propogation delay as each other and the same propagation delay under all conditions then your teacher is right.

When \$A\$ goes from 0 to 1, \$A\$ and \$\overline{A}\$ will both briefly be 1 at the same time, the output of the first level gates will therefore always contain at least one zero and there will be no glitch in the final output.

On the other hand when A goes from 1 to 0, \$A\$ and \$\overline{A}\$ will both briefly be 0 at the same time causing all three of the first stage gates to briefly output a 1 at the same time causing a glitch in the final output.

But those are IMO unwarranted assumptions. Propagation delays vary between gates, between different inputs on the same gate and with the direction of the transition. Depending on how other logic in the system is designed \$A\$ may in fact be generated from \$\overline{A}\$ rather than vice versa.

In the more general case where signals arriving on different paths could arrive in any order there could be a glitch in either direction (or if you get really unlucky a glitch in both directions).