Symbols for ep3c5e144 and ep3c25e144 in Eagle

You want to reduce the number of corners and straighten up some of your components.

1. The trace from R1 heading downwards wants moving a fraction left to remove the kink as it comes out of the resistor.

2. C2 can be moved up, and the two parallel traces from the negative pin can be combined into one.

3. D1 can move a fraction right to get rid of that little 90 degree bend as the trace from the 4561 pin 3 enters it.

I have marked them on your picture:

Some other thoughts:

• You may also want to have your corners at 45 degrees, not 90 degrees (mitre). I'm not entirely certain why people do this, but I for one think it looks nicer. You could of course break with all convention and use "Any Direction" lines, but I think that looks amateurish.

• You have a lot of wasted board space. Board costs money. The smaller your layout, the less board you use, the cheaper it costs.

• If you're thinking of etching this yourself, you may want to think about fattening up your traces a little to ensure they transfer properly and etch well.

Oh, and most importantly:

• Where are your inputs and outputs? I see the core of the circuit, but no Vcc, no GND, and no HIN/LIN/SD to the chip.

What you are doing is correct. The key part is the synchronizer. If the only inter-clock domain nets are processed there, you can ignore the warning.

Your plan to remote constraints on other nets isn't the right plan. If you get warnings apart from your synchronizer, that means you have clock crossing elsewhere. You need to fix them.