Tm4c nested uart interrupts- does each com finishes it’s run before the next one executed

What you are doing is quite normal and it should be possible to get it to work correctly.

The M4 processors have several dozen interrupt sources and it is very common for 2 or more interrupt requests (IRQ's) to become active at the same time. The IRQ's are "latched" by the interrupt logic and the interrupt controller decides on the basis of priority which one to process first (by vectoring to the interrupt handler). The 2nd IRQ is still latched, and is termed a "pending interrupt". In simple terms when an interrupt handler has completed its processing it has to execute a special instruction called a "return from interrupt" which allows the interrupt controller to process the next pending IRQ.

Although we sometimes talk about "stacked interrupts" in a situation like yours, they are not kept on a "stack" as such, and so it cannot run out of space and loose IRQ's. Generally the IRQ's remain latched until the corresponding IRQ bit is cleared by software.

It is difficult to know exactly why your system is locking up, you may have to provide more details. A couple of things to look at:

1. Is your interrupt handler always clearing the corresponding IRQ flag? If the flag is not cleared then the processor can get locked in a loop constantly vectoring to the handler and not allowing other things to run.

2. Does your interrupt handler always exit correctly by executing a "return from interrupt" special instruction? If it does not then it will not allow the interrupt controller to handle another IRQ at the same priority level, and it will appear that your processor is no longer responding to these interrupts.