Verilog only assigns first bit of a bus

busquartusregisterverilog

I'm trying to assign a 12bit parallel bus to a 12bit register. I've reduced the problem to this literal assignment but as with the previous case, only the first bit is being written to anything when I check the output. I've isolated the problem to this section, I can change the first bit data[0] but nothing else regardless of order.

Obligatory sketchy verilog:

input [11:0] ADC_bus;
...
always @(posedge SPIClock)
begin
    count = count + 1;
    if (count == 32)
    begin
        ADC_data[0] <= 1'b1;
        ADC_data[1] <= 1'b1;
        ADC_data[2] <= 1'b1;
        ADC_data[3] <= 1'b1;
        ADC_data[4] <= 1'b1;
        ADC_data[5] <= 1'b1;
        ADC_data[6] <= 1'b1;
        ADC_data[7] <= 1'b1;
        ADC_data[8] <= 1'b1;
        ADC_data[9] <= 1'b1;
        ADC_data[10] <= 1'b1;
        ADC_data[11] <= 1'b1;
    end
    else if (count == 16)
        ADCss = 1;
    else if (count == 64)
    begin
        count = 0;
        ADCss = 0;
    end
end

Result: ADC_data[11:0] is always 1

Best Answer

Oops, I had a typo in the top level that caused quartus to not see the wire[11:0] DAC_data; declaration and instead assume it was an implied single bit wire without throwing a warning. Seems like a good failure mode.

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