ldolevel-translation
Could someone explain the voltage translation "Magic" that is happening in the circuit in the link below?
The YRPBRL78G13( blue on the left ) is a 5V design and the cc3000 module is a 3.3V design.
I can't understand how the arrangement of LDO and pullup (pulldown?) resistors would achieve voltage translation.
I've tried simulating this, and as far as I can tell this shouldn't work.
All help is appreciated!
Since you have only one input available, you will need a 4:1 mux.
The ISL43640 is a 4 to 1 analog multiplexor. It can tolerate inputs up to Vcc + 0.3 volts so you will want to operate it with a +5v supply. You will select which of the four inputs you want using the address lines ADD1 and ADD2, requiring two output lines from you microcontroller. The minimum high voltage for these is 2.4v, with a typical value of 1.4v, so you should not have a problem driving them with a 3.3v output.
The internal resistance of the mux is approximately 100 Ω @ 5v.
To create the level translator on the output, you could use a resistor divider with a ratio of 100 / 150 to get 150/250*5v = 3v. One could use the internal resistance of 100 ohms for the top half of the divider, and a 150 resistor for the bottom, but this would put a load of 250 ohms on the inputs, or 5 / 250 = 20 mA which is probably more than desired (since you didn't give any spec on the available current going into the inputs, which obviously depends on the output stages driving the four mux inputs).
So instead, using a divider of 1000 ohms and 1500 ohms drops the current required to 2 mA. Subtracting off the 100 ohms internal resistance, leaves 900 ohms for the top resistor (closest 1% is 909) and 1500 for the bottom, with the output of 1500/2509*5v = 2.98v taken from the junction (you should measure this first using a 5v in before tying it to your micro).
The miniscule amount of current required by you microcontroller's input pin will not affect the balance of the resistor divider.
The part is available from Digi-Key for $2.64.
In the design you show, the gm of the output stage will be dependent upon the load current and so will affect the loop gain and potentially stability. Providing a minimum load will reduce the variation in gm and allow a better compromise in the feedback compensation.
Why do you have a capacitor to ground at the output of the amplifier - that will tend to make stability worse by introducing a pole in the transfer function.
Many voltage regulators have minimum load constraints for a different reason. Three pin regulators such as LM317 intentionally divert most of their internal operating current to the output in order to keep the current into the adjust pin constant. This means that if the output current falls below the operating current of the internal circuitry LDO will lose control and the output voltage will rise.
Best Answer
Another possibility could be that the pins on J1 that interface with J4 are not really 'outputs'. If its in a tristate/input or if its driven low (yes this is an output), then J4 never sees anything to do with 5V. Its all done via the the 10k pull up and J1 since little current through its pins.
Because J1 is a 5V device, as Ignacio Vazquez-Abrams pointed out, the threshold for a HIGH would be about 2.2V which and since the J5 would ouput 3.3V, its enough.