Why do dual-rank DIMMs have twice the bandwidth of quad-rank DIMMs?

I can't speak about FRAM (ferroelectric memory), but any technology that uses floating gates to store charge — any form of EPROM, including EEPROM and Flash — relies on electrons "tunneling" through a very thin insulating silicon oxide barrier to change the amount of charge on the gate.

The problem is that the oxide barrier is not perfect — since it is "grown" on top of the silicon die, it contains a certain number of defects in the form of crystal grain boundaries. These boundaries tend to "trap" the tunneling electrons more or less permanently, and the field from these trapped electrons interferes with the tunneling current. Eventually, enough charge is trapped to make the cell unwritable.

The trapping mechanism is very slow, but it is enough to give the devices a finite number of write cycles. Obviously, the number quoted by the manufacturer is a statistical average (padded with a safety margin) measured over many devices.

It is the clock frequency, i.e. frequency of the switching, and the number of transistors actually being switched at the same time that consume the power, and consequently, generate the heat, and not the number of transistors.

For example there could be a large amount of transistors in a area of the die that aren't being used, and so, if they are in the off (closed) state, then they will not draw any current, so less energy and less heat.

However, if some active area is switching at a higher clock frequency, then (on average) they are open for more of the time, and so draw more current, thus energy and heat.

Hope that helps.