Why is a capacitor placed in parallel with oscillator output

capacitoroscillator

I have a circuit board with an oscillator and I'm curious about why there is a capacitor hooked up to the output. The oscillator is a SWO series HCMOS Square Wave output crystal oscillator. The schematic of the oscillator connections is as follows. 

               +3.3V
                |
   ---------    |  C=0.01uF
NC-| 1   4 |---------||-----GND
   |       |
GND| 2   3 |---------->Direct to FPGA input pin
   ---------    |
                |
                = C=15pF
                |
               GND

The data sheet (select H22/H32/H53/SWO) does not reveal much, but there is a "Load" section that says the max load is 15pF. Specifically, it says:

Load | 15 pF ; ( 30 pF and 50 pF load are also available for +3.3V and +5.0V VDD)

In such a circuit, is the load the capacitor or the FPGA input pin? If the load is the capacitor, why is the load needed for the oscillator? What is its purpose?

Best Answer

They have a technote paper on this subject, "Effect of Load Capacitance on the Crystal":

http://www.mecxtal.com/pdf/te_notes/tn-021.pdf

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