Why is pin diagram of 7402 NOR gate reversed as compared to other gates

logic-gatespins

The following is a picture of pin design of 74 series TTL IC Family logic gates taken from this site:

We observe that in every logic gate, the input pins are (1,2), (4,5), (9,10), (12,13) and output pins are (3), (6), (8), (11) but in case of 7402 NOR gate, the input and output pins are reversed i.e. input pins are (2,3), (5,6), (8,9), (11,12) and output pins are (1), (4), (10), (13). Why is this so? Why is the pins reversed in case of 7402 NOR gate? The following picture clearly depicts what I am trying to say(taken from this datasheet):

Is it due to structural planning, stability or some other reason?The I couldn't find any reasoning on the internet and need some help. Also, what would happen if we connect NOR gate as we do in other gates?

Best Answer

We observe that in every logic gate, the input pins are (1,2), (4,5), (9,10), (12,13) and output pins are (3), (6), (8), (11) but in case of 7402 NOR gate, the input and output pins are reversed

Er, no we don't. The 74266 doesn't follow the supposed 'standard' pinout. Also the 7401 Quad Open Collector NAND, 7439 Quad Open Collector NAND, 7428 Quad NOR and 7433 Quad Open Collector NOR gates all have the same pinout as the 7402.

I suspect the original reason for the different pinouts was to get the most efficient layout on the chip.

Here's an annotated photo of a 7400 die:-

And here's a 74LS01:-

We observe that they are laid out in opposite directions relative to VCC and GND, which explains the different pinout. The fact that several gates followed the same layout as the 7401 suggests that there was an advantage to doing it in this direction.

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It's definitely a 3-input NOR gate.

P V T A
0 0 0 1
1 X X 0
X 1 X 0
X X 1 0

Why Cascaded NOT Gates Aren’t Used as Frequently as Flip-Flops

This circuit:

schematic

^{simulate this circuit – Schematic created using CircuitLab}

is inconvenient to use as a memory element. Because, how do you change its state ? If the output is 0 and I want to load a 1 it will be a contest between me feeding the 1 at the input and the output wanting to keep it 0.

If I'd use a very strong driver to drive the input it would always "win" but how would that store the bit ? It would not, the output of this circuit would simply follow the input, it would behave as a buffer.

A solution is to use a Tri-state output to drive this circuit, then in the "open" state of the strong driver (which drives the input) the bit would be remembered.

Still a stronger driver is needed and this is inefficient and there's a better way. Make the output of NOT2 also tri-state. Then when the memory needs to be written, make the output of NOT2 highZ and apply data at the input. Of course again the input must be driven with a tri-state output also but it does not have to be "strong" as NOT2's output will do nothing when the data is written.

In practice this kind of circuit (but with the tri-state outputs) is used only inside flip flops. Something like this:

Sorry that this is a blurry picture, it's the best I could find. I have better ones but I cannot share those (they are commercial designs).

The 4 transistors on top of each other (2 PMOS + 2 NMOS) are basically inverters (NOT gates) with a tri-state (high Z) option. Note how the 2 stacks of 4 transistors on the right side "bite eachother's tail" just like in your schematic. That is the memory cell !

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