You can't. Your system is not a linear map. In general, a transfer function can only be derived from a system that's linear and time-invariant (LTI). The constant term violates this linearity.
Specifically, the requirements for a linear map are:
1) \$y(x_1 + x_2)=y(x_1)+y(x_2)\$ (additive)
2) \$y(a x)=a y(x)\$ (homogeneous)
If you plug-n-chug into both equations, the violation should be clear:
\$y(x)=mx+5\$
1)
\$y(x_1)=mx_1+5\$, \$y(x_2)=mx_2+5\$, \$y(x_1)+y(x_2)=mx_1+mx_2+10\$
\$y(x_1+x_2)=m(x_1+x_2)+5=mx_1+mx_2+5 \neq y(x_1)+y(x_2)\$
2)
\$y(ax)=max+5\$
\$ay(x)=a(mx+5)=max+5a\neq y(ax)\$
Bisg is an INPUT signal not an INOUT despite the fact that it has other uses (driving segment G on the top level).
To see this; reflect that NOTHING in your component actually drives BISG.
So your component is regarded as driving it with an undefined initial level; that is, 'U', and the combination of that 'U' with any external driving level is - as ISIM says - 'U'.
You have 2 options to fix it:
(1) make BISG an INPUT since you aren't driving it. This is the simplest and in this case correct.
(2) Drive BISG in your component with 'Z' - that is, remove the 'U' output from the component. 'Z' means "high impedance : i.e. don't fight whatever external source (your testbench) is driving the pin. This is typically done to allow 2-way communication on a signal. The two ends must agree (somehow) which end is allowed to drive the signal and the other end must drive 'Z'.
In your case, adding the line
BISG <= 'Z';
(after the "begin") to your component BCT should resolve the problem. (Yes, you are modifying the file labelled "do not modify", and the modification WILL disappear when you next compile the schematic to VHDL).
Then re-run the simulation and all should be well.
I do not know if there's a way to implement solution 2 in the schematic - and I don't care : these days the schematic approach is an utter waste of time.
Your whole schematic comes down to (the original entity, and)
architecture HDL of BCT is
begin
Bisg <= 'Z';
Bnisc <= not Bisg;
sf <= not Bisg and not A;
saisdise <= Bisg or not A;
sb <= '1';
end HDL;
And simplifies further if Bisg is an input...
Which do you think is faster to create, and easier to read?
EDIT : if you need an output to drive segment G, there's nothing wrong with a separate port G, driven directly from input B, as G <= B; or a wire on the schematic.
Best Answer
The principle here is that you can't get information from nothing. If a function throws away information, the inverse function would need to magically reproduce it. In this case, your function is throwing away the sign of the input value. Let's look at two examples. In the first, x[n] = 1 for all values of n:
$$x[n-1] = 1$$ $$y[n] = \frac 1 {x[n-1]^2} = \frac 1 {(1)^2} = 1$$
In the second example, x[n] = -1:
$$x[n-1] = -1$$ $$y[n] = \frac 1 {x[n-1]^2} = \frac 1 {(-1)^2} = 1$$
In both cases, y[n] = 1.
Now, imagine that you're told y[n] = 1, and you want to find x[n]. How can you tell which of the two example sequences to choose? You can't. The difference between them is the sign, but squaring the input gets rid of the sign! Thus, the function is not invertible.