Dell PowerEdge – Advanced ECC vs Optimized for 8GB RAM

Just ran into the same problem with an R310. Took quite a bit of digging but the link to the R310 Tech Guide helped. The 1GB UDIMM uses 128Mb x8 chips which is why it works. The Samsung sticks they keep sending you use 256Mb x8 chips and as you found in the Tech Guide the R310 won't work with 256Mb chips. I ran into the same problem using some memory we pulled out of an R710 server but they were 256Mb x4 chips so it was a double no-no.

Here is what I've found regarding memory. The actual DRAM chips on the memory module have differing numbers of lines. This is also referred to as the rank width, e.g., x4, x8, x16. The DRAM chips are also different sizes, e.g., 128Mb, 256Mb, 512Mb. The easiest way to explain ranks is to think of each rank as a virtual DIMM. So a single rank module is just that; a single memory module on a single physical DIMM. Dual rank memory actually has 2 memory modules on a single physical DIMM (it's deeper than that but this is the easiest way to visualize it).

So the bottom line is that the R310 will only accept DIMMs that are made out of 128Mbit or 1Gb/2Gb chips that are x8 devices. Or at least that's my story and I'm sticking with it until Dell tells me otherwise; e-mail to them is out and I'll let you know if they say something different.

Link to Hynix part: http://www.hynix.co.kr/datasheet/eng/module/details/module_20_HMT112U7BFR8C.jsp?searchType=2&menuNo=1&m=1&s=1&RK=20&RAM_NAME=

A link to an excellent briefing from Intel: http://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&ved=0CDsQFjAB&url=http%3A%2F%2Fdownload.intel.com%2Feducation%2Fhighered%2Fsignal%2FELCT865%2FClass2_21_lab_and_project_assignment3.ppt&ei=VKOiT-yKDoau9AS86730CA&usg=AFQjCNHOMlxRyI0C8F7GIdwMkU8h1ZOmyQ&sig2=nLNmplaHcJjbv7rktoqb2Q

Slide 13 is the key, but the entire package is very good depending on your level of geekdom :)

Update: Confirmed with Dell except that I was wrong about requiring 128Mb and smaller chips. The Foxhollow platform does support 1Gb and 2Gb chips. See here: http://cache-www.intel.com/cd/00/00/43/26/432686_432686.pdf

It does make a difference, it will only make sense if you require the RAS (Reliability, Availability, and Service) features on x4 or x8 devices and understand the trade-offs for your needs. More details can be explained in the Dell white paper Dell™ PowerEdge™ Servers 2009 - Memory.

Also, configuration and layout with details specific to the R710 are available on the Technical Guidebook for the PowerEdge R710 - (Google this because I don't have reputation for link).

The important issue to note is the difference between ECC on the chip and the "Advanced ECC" provided by Dell's BIOS for Single Device Data Correction (SDDC). You will have a performance impact on both. The ECC will recover from errors during writes to the chip. However, SDDC goes a step further and will organize the bits so that an entire chip can fail and still be recoverable. See an example and details SDDC E7500 Chipset

The issues is whether your performance and/or reliability are of the utmost concern in your specific usage of the machine. If a chip failure will cause a loss of critical data or usage on this machine and it's non-redundant in the implementation, Advanced ECC may be a great way to go. However, you do so at a performance impact which may be more important to you.

I've implemented both in the field on Dell PowerEdge servers for single Microsoft SQL Server implementations. If I can be of more help, just comment to let me know.

Hope that helps.

EDIT: Coverage gap / ECC implementations

Yes, there is a coverage gap even if you implement both. Since, you are specifically using a cluster of high availability servers, IMHO you should use the Advanced ECC. Your performance impact is minimal compared to the benefits for the clustered devices. According to Crucial you have only a 2% decrease in performance on ECC memory in general.

The gap would be more specific to the types of errors that occur and how each handles the errors. In your specific situation it shouldn't translate to data loss. Since this is an Enterprise DBMS and errors, concurrency issues, etc. are managed at the software level in order to prevent data loss. A detailed history is kept of changes in a properly configured DBMS and the software that uses it can typically setup to have the transaction "rollback" any if a severe error occurs.

ECC Implementations

ECC will attempt to correct any bit errors in memory read/write. However, if the error is more significant, then not even ECC will be able to recover, causing potential loss of data. There is more discussion on ECC as well at ServerFault/What is ECC ram and why is it better?

According to Wikipedia on ECC_Memory

ECC memory maintains a memory system effectively free from single-bit errors...

SDDC

If you refer to the E7500 chipset document above (note the 55xx/56xx from Intel require login/partnership but the idea is similar which is why I didn't link originally), which describes SDDC and how it's made possible. Basically, it uses a technique for organizing the words written to memory that ensures all are written in such a way that every word will only contain a single bit error i.e. the word should be recoverable from the single bit error (as above). Now that's per word, so it could potentially recover from up to 4-bit errors on x4 devices (1 per word) and up to 8-bit errors on x8 devices (still 1 per word) by error correcting each word.

Additional errors, more bit errors, total memory failure, channel failure, bus failure, etc. can still all cause horrible problems but that's why you have a cluster and an Enterprise DBMS.

In short, if you have everything enabled and there's too many bit errors for error correction algorithms to correct you will still have an error i.e. error coverage gap. These can be exceptionally rare though.