Fetching instructions from memory

You will probably make it a lot easier on yourself and avoid a lot of user errors if you allow the declaration of variable-length arrays to be delayed until a point where the size is known. Then you don't have to invent a syntax for assigning the array size and you don't have to deal with differences in the order in which arrays are declared and in which they get their size.

If your compiler uses a stack-based allocation scheme for local variables (they are given addresses relative to the stack-frame of their function, like it is done for the 'big' platforms), the variable-length arrays can just be carved out of the stack frame as needed. Only if there are multiple variable-length arrays in a function do you need an additional pointer to indicate where the data of each starts.

If your compiler uses a fixed allocation scheme (all variables, including locals, are given a fixed (absolute) address by the compiler/linker), I would use an 'array stack' for carving the variable-length arrays from. As overhead, you would need a global pointer to indicate where the free space currently starts, a pointer for each variable-length array to indicate where its data is located and, in each function using variable-length arrays, a way to restore the global pointer to the value it had when entering the function.
The user would also need some way to indicate to the compiler/linker how much of a 'array stack' he thinks will be needed. A reasonable default could be to use whatever is left after allocating all fixed-size variables and variable-length array overhead.

I think this scheme uses the least amount of overhead, both space and time-wise. The scheme you came up with is essentially a malloc implementation.

It depends.

Some (CISC) CPUs have byte-wise loads that can address individual bytes so the byte of interest is the low-order 8-bits on the bus; the rest of the bits are masked off.

Many RISC CPUs will do word-load, barrel shift, while others will do word-load, bit shift and in the middle, are ones that do word-load, byte shift.

Some CPUs will do consecutive word-loads when a two-byte value spans a 32-bit boundary, shifting and masking the words together.

CPU families may do different implementations depending on the particular processor model. That explains why there is no description of the implementation; it's a decision only the vendor cares about.

As for performance, you will just have to test it on the particular CPU and memory configurations you care about.