Memory – How Does the CPU Know When It Received RAM Data?

cpumemory

Well, the title is pretty much self explanatory, but I'll expound it a bit, and say the origin of my question.

So, I've been wondering as to how the CPU knows when it received the RAM. I'm pretty sure it doesn't OR the RAM outputs together, because 0x00 is still a number, yet ORing that together says that the RAM has not outputed anything. Does the RAM have some kind of "request acknowledged" line? Well, my friend was making an MC CPU, and he used interrupts for RAM reading, so that's where I got this idea.

Anyways, the origin of my problem is probably when I was thinking about Virtual Memory. In virtual memory, you have to fetch from the disk and to the RAM. How does one compensate for the gap between the speeds? May this be answered too?

Best Answer

Yes, there is a Data Acknowledge signal. It asserts that the data has been placed onto the memory bus, and is available to the processor for reading.

Briefly, the memory read cycle works like this:

The processor initiates a read bus cycle by floating the address of the memory location on the address lines.
Once the address lines are stable, the processor asserts the address strobe signal on the bus. The address strobe signals the validity of the address lines.
The processor then sets the Read/Write signal to high, i.e. read.
Now the processor asserts the data strobe signal. This signals to the memory that the processor is ready to read data.
The memory subsystem decodes the address and places the data on the data lines.
The memory subsystem then asserts the data acknowledge signal. This signals to the processor that valid data can now be latched in.
The processor latches in the data and negates the data strobe. This signals to the memory that the data has been latched by the processor. The processor also negates the address strobe signal.
Memory subsystem now negates the data acknowledgement signal. This signals the end of the read bus cycle.

The Data Acknowledge signal is asserted in Step 6.

Processors compensate for the amount of time it takes to read memory by imposing Wait States. However, virtual memory is an operating system function, so the operating system manages the time it takes to read the data off the hard disk and swap it into memory, where the CPU can read it in the usual way.

In simple terms, the CPU simply waits in a loop until the data is available.

Related Solutions

Why are there separate L1 caches for data and instructions

There are actually several reasons.

First and probably foremost, the data that's stored in the instruction cache is generally somewhat different than what's stored in the data cache -- along with the instructions themselves, there are annotations for things like where the next instruction starts, to help out the decoders. Some processors (E.g., Netburst, some SPARCs) use a "trace cache", which stores the result of decoding an instruction rather than storing the original instruction in its encoded form.

Second, it simplifies circuitry a bit -- the data cache has to deal with reads and writes, but the instruction cache only deals with reads. (This is part of why self-modifying code is so expensive -- instead of directly overwriting the data in the instruction cache, the write goes through the data cache to the L2 cache, and then the line in the instruction cache is invalidated and re-loaded from L2).

Third, it increases bandwidth: most modern processors can read data from the instruction cache and the data cache simultaneously. Most also have queues at the "entrance" to the cache, so they can actually do two reads and one write in any given cycle.

Fourth, it can save power. While you need to maintain power to the memory cells themselves to maintain their contents, some processors can/do power down some of the associated circuitry (decoders and such) when they're not being used. With separate caches, they can power up these circuits separately for instructions and data, increasing the chances of a circuit remaining un-powered during any given cycle (I'm not sure any x86 processors do this -- AFAIK, it's more of an ARM thing).

Computer Science – How Do Lines of Code Get Executed by the CPU?

The lines of code have nothing to do with how the CPU executes it. I'd recommend reading up on assembler, because that will teach you a lot about how the hardware actually does things. You can also get assembler output from many compilers.

That code might compile into something like (in a made up assembly language):

load R1, [x] ; meaning load the data stored at memory location x into register 1
add R1, 5
store [x], R1 ; store the modified value into the memory location x
sub R1, 3
store R1, [y]

However, if the compiler knows that a variable isn't used again, the store operation may not be emitted.

Now for the debugger to know what machine code corresponds to a line of program source, annotations are added by the compiler to show what line corresponds to where in the machine code.

Best Answer

Related Solutions

Why are there separate L1 caches for data and instructions

Computer Science – How Do Lines of Code Get Executed by the CPU?

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