Calling existing make command in cmake file

cmakemakefile

I have a large project with multiple subdirectories. In the parent directory, I have a CMakeLists.txt file which calls functions defined in other cmake files in the same parent directory. I have a custom Makefile in one of the subdirectories that contains some target "run". When I call cmake from the parent directory, I want the "run" target located in the subdirectory makefile to execute. How should I do this? I understand that some people have suggested to use add_custom_target and add_custom_command, but I am still confused as to how to apply these commands to accomplish this task.

Best Answer

If you know, which file(s) are produced by Makefile in the subdirectory, and want to depend on these files, use add_custom_command:

add_custom_command(OUTPUT <output-file>
                   COMMAND make run
                   WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/<subdir>
)

This assumes that your CMakeLists.txt have a target, which depends or uses given file.

Otherwise, if you do not care which files are produced by Makefile, use add_custom_target:

add_custom_target(<target_name> COMMAND make run
                   WORKING_DIRECTORY ${CMAKE_CURRENT_SOURCE_DIR}/<subdir>
)

In both cases WORKING_DIRECTORY specifies directory which should be current for command executed.

If you want the target (in the second case) to be executed by default, add ALL option before the COMMAND.

Related Solutions

Passing additional variables from command line to make

You have several options to set up variables from outside your makefile:

From environment - each environment variable is transformed into a makefile variable with the same name and value.

You may also want to set -e option (aka --environments-override) on, and your environment variables will override assignments made into makefile (unless these assignments themselves use the override directive . However, it's not recommended, and it's much better and flexible to use ?= assignment (the conditional variable assignment operator, it only has an effect if the variable is not yet defined):
```
FOO?=default_value_if_not_set_in_environment
```
Note that certain variables are not inherited from environment:
- MAKE is gotten from name of the script
- SHELL is either set within a makefile, or defaults to /bin/sh (rationale: commands are specified within the makefile, and they're shell-specific).
From command line - make can take variable assignments as part of his command line, mingled with targets:
```
make target FOO=bar
```
But then all assignments to FOO variable within the makefile will be ignored unless you use the override directive in assignment. (The effect is the same as with -e option for environment variables).
Exporting from the parent Make - if you call Make from a Makefile, you usually shouldn't explicitly write variable assignments like this:
```
# Don't do this!
target:
        $(MAKE) -C target CC=$(CC) CFLAGS=$(CFLAGS)
```
Instead, better solution might be to export these variables. Exporting a variable makes it into the environment of every shell invocation, and Make calls from these commands pick these environment variable as specified above.
```
# Do like this
CFLAGS=-g
export CFLAGS
target:
        $(MAKE) -C target
```
You can also export all variables by using export without arguments.

Linux – How to use CMAKE_INSTALL_PREFIX

That should be (see the docs):

cmake -DCMAKE_INSTALL_PREFIX=/usr ..

Best Answer

Related Solutions

Passing additional variables from command line to make

Linux – How to use CMAKE_INSTALL_PREFIX

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