If Statement VHDL

hardwareif statementvhdl

Can some one explain why the golden rule when writing VHDL is that the if-then-else statement must be in a process. Is it because inside the process, the statements are executed sequentially, while outside they're not.

Best Answer

The simple answer is "because that's how the syntax of the language is"!

If you want to select from some options with code not in a process you can do:

sig <= a when sel = 1 else
       b when sel = 2 else 
       default_value;

or

with sel select
   sig <= a when 1,
          b when 2,
          default_value when others;

See here for many examples of a mux

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