MIPS synchronisation (ll/sc)

mipssynchronization

I wanted to know that if while using ll/sc there is a change in processor before the sc statement is executed what would be result.

E.g.

CPU 1 ==> $t1 = 1, $t0 = 2

CPU 2 ==> $t1 = 30, $t0 = 40

MEMORY ==> $s0 = 99

If we execute these statements:

ll $t1, 0($s0)    # CPU 1
ll $t1, 0($s0)    # CPU 2
addi $t1, $t1, 1  # CPU 2
sc $t1, 0($s0)    # CPU 2 ($t1 = 1, $s0 = 100)
sc $t0, 0($s0)    # CPU 1

I know that after the execution (Correct me if I am wrong):

CPU 2 ==> $t1 = 1, $t0 = 40

CPU 1 ==> $t1 = 99

I don't know what will happen to $s0 and $t0 after the last CPU 1 command. Will $s0 = 2 ??

Best Answer

Alright...I found the solution myself... As there has been a change in CPU from when the ll statement was first executed on CPU1 and that CPU2 is modifying the same memory region, so sc in line 5 (last line) would fail. So when sc fails $t0 = 0 & as memory is not modified due to sc failure in last line so $s0 = 100

Source: http://www.weblearn.hs-bremen.de/risse/RST/docs/MIPS/mips-isa.pdf

Read Load Linked (LL) and Store Conditional (SC) extracts.

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